Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer

Patent metadata

Field	Value
Publication number	US-9501280-B2
Application number	US-201414194589-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Nov 14, 2006
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.

First claim

What is claimed is:

1. A system, comprising:
a cache adapted to store a prefeteched value for a consuming instruction, wherein the cache associates the prefeteched value with a corresponding name and wherein the consuming instruction explicitly references the corresponding name instead of a memory address, wherein the corresponding name is a label associated with a load address calculation instruction within a program that is executed to obtain the prefetched value; and
a scheduling unit to issue the consuming instruction after the prefetched value is loaded in the cache and to release the location of the prefeteched value in the cache after an execution unit executes the consuming instruction using the prefetched value.

2. The system of claim 1 wherein the corresponding name indicates a source of dependency for the consuming instruction.

3. The system of claim 1 wherein the scheduling unit confirms that the prefetched value is validly loaded from higher memory prior to the execution unit executing the consuming instruction.

4. The system of claim 1 wherein a context switch in response to a call to an exception handler or a system call is used to release the location of the prefetched value.

5. The system of claim 1 further comprising physical registers with flag fields to facilitate conditional execution of an instruction and delay slots for branch instructions.

6. The system of claim 1 further comprising an instruction fetch unit to selectively execute a conditional branch instruction in response to an evaluation of a flag field.

7. A system as claimed in claim 1 wherein
the cache is adapted to store a sequence of prefetched values corresponding to a sequence of consuming instructions, wherein the sequence of prefetched values has a single corresponding name regardless of the number of prefeteched values;
wherein the execution unit is adapted to execute the sequence of consuming instructions using the sequence of prefetched values; and
wherein the scheduling unit is adapted to release the locations of the sequence of prefeteched values in the cache after the execution unit executes the sequence of consuming instructions.

8. The system of claim 7 wherein the sequence of prefetched values is used to access an array inside a loop.

9. The system of claim 7 wherein the scheduler resets a write counter in an inheritance vector when the sequence of prefeteched values is allocated.

10. The system of claim 8 wherein the scheduler increments the write counter for every iteration of a loop.

11. The system of claim 7 wherein the scheduler maintains a read counter for each consuming instruction.

12. The system of claim 11 wherein the scheduler increments the read counter for each consuming instruction read from the sequence of consuming instructions.

13. The system of claim 7 wherein the cache stores the sequence of prefetched values without performing ordering checks.

14. The system of claim 13 wherein the scheduler performs an ordering check with respect to stores when a consuming instruction executes.

15. The system of claim 14 wherein the scheduler includes a bypass mechanism to selectively fetch a stored value instead of a prefetched value.

16. The system of claim 7 wherein the execution unit speculatively executes a consuming instruction ahead of a stored instruction through thread control speculation.

17. The system of claim 16 wherein the execution unit conditionally executes a prefetch thread on an ordering check made upon execution of a preceding store.

Assignees

• Soft Machines Inc

Inventors

• Abdallah Mohammad A

Classifications

• G06F9/342

  Extension of operand address space · CPC title

• G06F9/30138

  Extension of register space, e.g. register cache · CPC title

• G06F9/3891

  organised in groups of units sharing resources, e.g. clusters · CPC title

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/462

  with multiple register sets · CPC title