Information processing apparatus, information processing method, and computer program product

US9354923B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9354923-B2
Application numberUS-201414198029-A
CountryUS
Kind codeB2
Filing dateMar 5, 2014
Priority dateJun 18, 2013
Publication dateMay 31, 2016
Grant dateMay 31, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

According to an embodiment, an information processing apparatus includes a banked register determiner and a saving register determiner. The banked register determiner is configured to hold register information indicating which of a banked register and a non-banked register a register which is used by the operating system is, receive an acquisition instruction for the non-banked or banked register and the information about the mode of the operating system, and return a list of the non-banked or banked registers. The saving register determiner is configured to acquire the mode in which the operating system is capable of operating, determine that saving of the banked register for the mode is necessary when another operating system is capable of operating in the mode, acquire a list of the banked registers, and acquire a list of the non-banked registers from the banked register determiner.

First claim

Opening claim text (preview).

What is claimed is: 1. An information processing apparatus where a plurality of operating systems are capable of operating in a plurality of modes, a register which is used by each operating system including a banked register whose area is allocated to each mode and a non-banked register shared by the modes, the apparatus comprising: an instruction detector configured to issue a first request for switching the operating systems when detecting a switching instruction regarding the operating systems; a switcher configured to issue a second request for saving and restoring the register when the switching instruction is detected, the second request specifying the operating system that is a switching source and the operating system that is a switching destination that are included in the first request; a save information manager configured to hold information about the mode in which the operating system is capable of operating, and information about the banked register and the non-banked register that are saved at a time of switching, among the registers used by the operating system; a banked register determiner configured to hold register information indicating which of the banked register and the non-banked register the register is, receive an acquisition instruction for the non-banked register or the banked register and the information about the mode, and return a list of the non-banked registers or a list of the banked registers used in the received mode; a saving register determiner configured to acquire the mode in which the operating system that is the switching source is capable of operating from the save information manager, determine that saving of the banked register for the mode is necessary when the operating system that is the switching source is capable of operating in the acquired mode, and when another operating system is capable of operating in the mode, acquire a list of the banked registers that need to be saved by transferring the information about the mode to the banked register determiner, and acquire a list of the non-banked registers from the banked register determiner; and a register saver/restorer configured to, in response to the second request, acquire the lists of the banked registers that need to be saved and the non-banked registers from the saving register determiner, acquire, from the save information manager, information about the register to be restored that was saved at a time of previous switching in the operating system that is the switching destination, and save and restore the register. 2. The apparatus according to claim 1 , wherein the saving register determiner is configured to receive information about whether a process interruption for the operating system occurs or not in the mode, and determine that saving of the banked register for the mode specified is unnecessary when the operating system that is the switching source is capable of operating in the mode at a time of the first request, when another operating system is capable of operating in the mode, and when the information received from the operating system that is the switching source indicates that there is no possibility of the process interruption. 3. The apparatus according to claim 1 , further comprising: an interrupt state manager configured to store settings regarding whether an interrupt is allowed or not for each mode of the operating system, and a state of an interrupt for each mode; an interrupt detector configured to detect occurrence of the interrupt and notify the interrupt state manager of start of an interrupt process at the operating system that is an interrupt input destination, and detect end of the interrupt and notify the interrupt state manager of end of the interrupt process at the operating system that is the interrupt input destination; and an interrupt policy determiner configured to detect a change in the settings regarding whether an interrupt is allowed or not, and update the interrupt state of the operating system that is the interrupt input destination, wherein the saving register determiner is configured to acquire, from the interrupt state manager, the interrupt state of a mode for performing an interrupt process at the operating system that is currently being processed, determine that saving of the banked register is unnecessary when an interrupt is being processed and when an interrupt by another operating system in the same mode is impossible, and determine that saving of the banked register is necessary when the mode is other than the mode for performing an interrupt process or when the operating system is processing an interrupt and another operating system in the same mode is allowed to perform an interrupt. 4. The apparatus according to claim 1 , further comprising: a plurality of processors; and a core manager configured to control the save information manager and the register saver/restorer for each of the processors. 5. The apparatus according to claim 3 , further comprising: a dynamic setting change detector configured to detect, for each operating system, a change in settings of whether operation in the mode is possible or not, and in settings of whether an interrupt is allowed or not for each mode, determine whether there is a possibility of the operating system that is a setting source destroying the banked register, and save the banked register when there is a possibility of destruction and when another operating system is using the banked register. 6. The apparatus according to claim 1 , wherein the saving register determiner is configured to receive, from the operating system, whether a security setting for the mode is valid or invalid, and determine that a value of the banked register needs to be cleared even when saving of the banked register is determined to be unnecessary when the security setting is valid, and the register saver/restorer is configured to clear the value of the banked register when clearing of the value of the banked register is determined to be necessary. 7. An information processing method for an information processing apparatus where a plurality of operating systems are capable of operating in a plurality of modes, a register which is used by each operating system including a banked register whose area is allocated to each mode and a non-banked register shared by the modes, the method comprising: issuing a first request for switching the operating systems when detecting an switching instruction regarding the operating systems; issuing a second request for saving and restoring the register when the switching instruction is detected, the second request specifying the operating system that is a switching source and the operating system that is a switching destination that are included in the first request; managing save information by holding information about the mode in which the operating system is capable of operating, and information about the banked register and the non-banked register that are saved at a time of switching, among the registers used by the operating system; determining the register by holding register information indicating which of the banked register and the non-banked register the register is, by receiving an acquisition instruction for the non-banked register or the banked register and the information about the mode, and by returning a list of the non-banked registers or a list of the banked registers used in the received mode; determining a saving register by acquiring the mode in which the operating system that is the switching source is capable of operating, by determining that saving of the banked register for the mode is necessary when the operating system that is the switching source is capable of operating in t

Assignees

Inventors

Classifications

  • using interrupt (G06F13/32 takes precedence) · CPC title

  • G06F9/462Primary

    with multiple register sets · CPC title

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Frequently asked questions

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What does patent US9354923B2 cover?
According to an embodiment, an information processing apparatus includes a banked register determiner and a saving register determiner. The banked register determiner is configured to hold register information indicating which of a banked register and a non-banked register a register which is used by the operating system is, receive an acquisition instruction for the non-banked or banked regist…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification G06F9/462. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).