Variable resistance memory devices

Patent metadata

Field	Value
Publication number	US-10256190-B2
Application number	US-201715809373-A
Country	US
Kind code	B2
Filing date	Nov 10, 2017
Priority date	Jan 20, 2017
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.

First claim

What is claimed is:

1. A device, comprising:
a substrate including a first memory region and a second memory region;
a first variable resistance pattern on the first memory region at a first height from the substrate, the first variable resistance pattern including
a first shape,
a first thickness, and
a first material; and

a second variable resistance pattern on the second memory region at a second height from the substrate, the second height less than the first height from the substrate, the second variable resistance pattern including
a second shape that is different from the first shape,
a second thickness that is different from the first thickness,
a second material that is different from the first material,
a sub-combination thereof, or
a combination thereof;

a first interconnection group on the substrate, the first interconnection group including a plurality of first interconnection patterns;
a second interconnection group between the substrate and the first interconnection group, the second interconnection group including a plurality of second interconnection patterns; and
a third interconnection group between the substrate and the second interconnection group, the third interconnection group including a plurality of third interconnection patterns,
wherein the first interconnection group, the second interconnection group, and the third interconnection group are at different heights from the substrate,
wherein the first variable resistance pattern is between the first interconnection group and the second interconnection group, and
wherein the second variable resistance pattern is between the second interconnection group and the third interconnection group.

2. The device of claim 1 , wherein,
the first variable resistance pattern is connected to one first interconnection pattern of the plurality of first interconnection patterns and one second interconnection pattern of the plurality of second interconnection patterns, and
the second variable resistance pattern is connected to a separate one second interconnection pattern of the plurality of second interconnection patterns and one third interconnection pattern of the plurality of third interconnection patterns.

3. The device of claim 2 , further comprising:
a first contact pattern on the second memory region, the first contact pattern between the first interconnection group and the second interconnection group; and
a second contact pattern on the first memory region, the second contact pattern between the second interconnection group and the third interconnection group,
wherein the first variable resistance pattern is connected to a separate one third interconnection pattern of the plurality of third interconnection patterns via the second contact pattern, and
wherein the second variable resistance pattern is connected to a separate one first interconnection pattern of the plurality of first interconnection patterns via the first contact pattern.

4. The device of claim 3 , wherein,
the first variable resistance pattern is electrically coupled to the substrate through the second contact pattern and the separate one third interconnection pattern of the plurality of third interconnection patterns connected to the second contact pattern, and
the second variable resistance pattern is electrically coupled to the substrate through the one third interconnection pattern of the plurality of third interconnection patterns connected to the second variable resistance pattern.

5. The device of claim 4 , wherein,
the first variable resistance pattern is configured to be controlled based on application of a voltage through the one first interconnection pattern of the plurality of first interconnection patterns connected thereto,
the second variable resistance pattern is configured to be controlled based on application of a separate voltage through the first contact pattern and the separate one first interconnection pattern of the plurality of first interconnection patterns connected to the first contact pattern, and
the first variable resistance pattern and the second variable resistance pattern are configured to be independently controlled.

6. The device of claim 1 , wherein,
the first variable resistance pattern and the second variable resistance pattern include a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern, respectively,
the first magnetic tunnel junction pattern is configured to switch magnetization direction based on a first critical current density, and
the second magnetic tunnel junction pattern is configured to switch magnetization direction based on a second critical current density, the second critical current density different from the first critical current density.

7. The device of claim 1 , wherein the first variable resistance pattern and the second variable resistance pattern are laterally spaced apart from each other on the substrate.

8. The device of claim 1 , wherein,
the first variable resistance pattern is included in a first memory cell on the first memory region, the first memory cell being a non-volatile memory (NVM) cell, and
the second variable resistance pattern included in a second memory cell on the second memory region, the second memory cell being a random access memory (RAM) cell.

9. A device, comprising:
a substrate including a first memory region and a second memory region;
a first variable resistance pattern on the first memory region at a first height from the substrate; and
a second variable resistance pattern on the second memory region at a second height from the substrate, the second height different from than the first height, the second variable resistance pattern including an intrinsic property that is different from a corresponding intrinsic property of the first variable resistance pattern;
a first interconnection group on the substrate, the first interconnection group including a plurality of first interconnection patterns;
a second interconnection group between the substrate and the first interconnection group, the second interconnection group including a plurality of second interconnection patterns; and
a third interconnection group between the substrate and the second interconnection group, the third interconnection group including a plurality of third interconnection patterns,
wherein the first interconnection group, the second interconnection group, and the third interconnection group are at different heights from the substrate,
wherein the first variable resistance pattern is between the first interconnection group and the second interconnection group, and
wherein the second variable resistance pattern is between the second interconnection group and the third interconnection group.

10. The device of claim 9 , wherein,
the first variable resistance pattern is connected to one first interconnection pattern of the plurality of first interconnection patterns and one second interconnection pattern of the plurality of second interconnection patterns, and
the second variable resistance pattern is connected to a separate one second interconnection pattern of the plurality of second interconnection patterns and one third interconnection pattern of the plurality of third interconnection patterns.

11. The device of claim 10 , further comprising:
a first contact pattern on the second memory region, the first contact pattern between the first interconnection group and the second interconnection group; and
a second contact pattern on the first memory region, the second contact pattern between the second interconnection group and the third interconnection group,
wherein the first variable resistance pattern is

Assignees

• Lee Yongkyu
• Koh Gwanhyeob
• Seo Boyoung
• Samsung Electronics Co Ltd

Inventors

• Lee Yongkyu
• Koh Gwanhyeob
• Seo Boyoung

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L45/06

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L23/528 Primary

  Electricity · mapped topic