Landing pad in peripheral circuit for magnetic random access memory (MRAM)

Patent metadata

Field	Value
Publication number	US-9373663-B2
Application number	US-201314033374-A
Country	US
Kind code	B2
Filing date	Sep 20, 2013
Priority date	Sep 20, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.

First claim

What is claimed is:

1. A memory device including:
a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) memory element having a variable resistance; and
a peripheral circuit region comprising:
a substrate and a bottom contact formed therein;
a landing pad formed on top of said bottom contact, said landing pad comprising a first magnetic layer structure and a second magnetic layer structure with a degraded insulating junction layer interposed therebetween, thereby allowing electric current to conduct through said landing pad; and
a via formed on top of said landing pad,
wherein neither said landing pad nor said via is directly connected to an MTJ memory element.

2. The device according to claim 1 , wherein said degraded insulating junction layer is made of magnesium oxide (MgO).

3. The device according to claim 1 , wherein said via is made of tungsten (W) or copper (Cu).

4. The device according to claim 1 , wherein at least one of said first and second magnetic layer structures is made of an alloy layer comprising cobalt (Co), iron (Fe), and boron (B).

5. The device according to claim 1 , wherein at least one of said first and second magnetic layer structures comprises a plurality of magnetic layers.

6. The device according to claim 1 , wherein one of said first and second magnetic layer structures comprises two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.

7. The device according to claim 1 , wherein one of said first and second magnetic layer structures comprises an anti-ferromagnetic layer and two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.

8. The device according to claim 1 , wherein each MTJ memory element comprises multiple magnetic layers having magnetization directions that are substantially perpendicular to respective layer planes.

9. A memory device comprising:
a memory cell region comprising a plurality of memory cells, each memory cell including a magnetic tunnel junction (MTJ) memory element having a variable resistance; and
a peripheral circuit region including:
a substrate and a bottom contact formed therein;
a landing pad formed on top of said bottom contact, said landing pad including at least a conductive layer and an insulating layer thereabove with an opening; and
a via partly embedded in said landing pad and directly coupled to said conductive layer through said opening,
wherein neither said landing pad nor said via is directly connected to an MTJ memory element.

10. The device according to claim 9 , wherein each MTJ memory element comprises multiple magnetic layers having magnetization directions that are substantially perpendicular to respective layer planes.

11. A memory device comprising:
a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) memory element having a variable resistance; and
a peripheral circuit region comprising:
a substrate and a bottom contact formed therein;
a landing pad comprising a first magnetic layer structure formed on top of said bottom contact and a second magnetic layer structure separated from said first magnetic layer structure by an insulating tunnel junction layer, each of said insulating tunnel junction layer and said second magnetic layer structure having an opening aligned to each other; and
a via partly embedded in said landing pad and directly coupled to said first magnetic layer structure through said openings,
wherein neither said landing pad nor said via is directly connected to an MTJ memory element.

12. The device according to claim 11 , wherein said degraded insulating junction layer is made of magnesium oxide (MgO).

13. The device according to claim 11 , wherein said via is made of tungsten (W) or copper (Cu).

14. The device according to claim 11 , wherein at least one of said first and second magnetic layer structures is made of an alloy layer comprising cobalt (Co), iron (Fe), and boron (B).

15. The device according to claim 11 , wherein at least one of said first and second magnetic layer structures comprises a plurality of magnetic layers.

16. The device according to claim 11 , wherein one of said first and second magnetic layer structures comprises two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.

17. The device according to claim 11 , wherein one of said first and second magnetic layer structures comprises an anti-ferromagnetic layer and two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.

18. The device according to claim 11 , wherein each MTJ memory element comprises multiple magnetic layers having magnetization directions that are substantially perpendicular to respective layer planes.

19. A memory device including:
a memory cell region comprising a plurality of memory cells, each memory cell including a magnetic tunnel junction (MTJ) memory element having a variable resistance; and
a peripheral circuit region comprising:
a substrate and a bottom contact formed therein;
a landing pad formed on top of said bottom contact, said landing pad comprising a conductive layer and a degraded insulating layer formed thereon, thereby allowing electric current to conduct through said landing pad; and
a via formed on top of said landing pad,
wherein neither said landing pad nor said via is directly connected to an MTJ memory element, wherein each MTJ memory element comprises multiple magnetic layers having magnetization directions that are substantially perpendicular to respective layer planes.

Assignees

• Avalanche Technology Inc
• Avalanche Technology Inc

Inventors

• Satoh Kimihiro
• Huai Yiming

Classifications

• H01L27/222 Primary

  Electricity · mapped topic

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10B61/10 Primary

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title