Electronic memory including ROM and RAM

Patent metadata

Field	Value
Publication number	US-9552859-B2
Application number	US-201514723450-A
Country	US
Kind code	B2
Filing date	May 27, 2015
Priority date	May 27, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each including, connected to a source line (SL), a series connection (in any order) of a selection element (e.g., transistor gated by word line WL), a resistive storage element (e.g., MTJ), and a permanent connection to one of the bit lines (e.g., BL 0 , BL 1 ). The apparatus may also include a ROM sense amplifier which is configured to precharge two output nodes connected to respective ones of the bit lines, so that the jumper in a selected memory cell pulls one of the output nodes to a first reference potential (e.g., GND) and the ROM sense amplifier pulls the other of the output nodes to a second reference potential (e.g., Vdd).

First claim

The invention claimed is:

1. A combination random-access memory (RAM) and read-only memory (ROM) electronic data-storage device, comprising:
at least two bit lines;
at least two current sources, each of the current sources connected to a corresponding one of the bit lines;
a plurality of bit cells, the bit cells each comprising a series connection of a selection element and a variably-resistive storage element, the bit cells each comprising a cell input node having a permanent connection to only one of the bit lines and a cell output node connected to a source line, the selection element having a control input connected to a word line;
a first sensing amplifier connected to a first one of the bit lines, the first sensing amplifier configured to output a first voltage when the first bit line is driven above a reference voltage and a second voltage when the first bit line is driven below the reference voltage;
a second sensing amplifier connected to a second one of the bit lines, the second sensing amplifier configured to output the first voltage when the second bit line is driven above the reference voltage and the second voltage when the second bit line is driven below the reference voltage.

2. The device according to claim 1 , wherein the selection element comprises a transistor.

3. The device according to claim 2 , wherein the transistor comprises a gate.

4. The device according to claim 3 , wherein the transistor gate is connected to a word line.

5. The device according to claim 1 , wherein the resistive storage element is a magnetic tunnel junction.

6. The device according to claim 1 , wherein the permanent connection between the bit cell and the bit line comprises a via.

Assignees

• Purdue Research Foundation

Inventors

• Roy Kaushik
• Lee Dongsoo
• Fong Xuanyao

Classifications

• G11C11/1659

  Cell access · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title