Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9330754-B2
Application number	US-201514960737-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Mar 6, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit line contacts.

First claim

What is claimed is:

1. A method for fabricating an electronic device including a semiconductor memory, comprising:
providing a substrate including a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction;
forming source line contacts alternately disposed over the active regions arranged in the first and second directions and disposed over the active regions arranged in a third direction intersecting the first and second directions;
forming source lines extending in the third direction and being coupled to the source line contacts;
forming contacts disposed over the active regions at locations where the source line contacts are not disposed;
forming variable resistance elements over the contacts so that the variable resistance elements are coupled to the contacts, respectively;
forming bit line contacts over the variable resistance elements so that the bit line contacts are coupled to the variable resistance elements, respectively; and
forming bit lines extending in a fourth direction intersecting the first to third directions and being coupled to the bit line contacts.

2. The method of claim 1 , wherein the word lines are formed by forming trenches by selectively etching the substrate and burying lower portions of the trenches with a conductive material.

3. The method of claim 1 , wherein the forming of the contacts is performed such that the contacts penetrate through interlayer dielectrics, wherein the interlayer dielectrics cover the source lines.

4. The method of claim 1 , wherein the forming of the contacts includes forming groups of contacts at different heights in the fourth direction.

5. The method of claim 4 , wherein the forming of the bit line contacts includes forming groups of bit line contacts which overlap the groups of contacts, respectively, and
upper heights of the groups of bit line contacts are the same.

6. The method of claim 1 , wherein the forming of the variable resistance elements includes forming a material layer including a ferromagnetic material, a ferroelectric material, a phase change material, or a metal oxide, and selectively etching the material layer.

7. A method for fabricating an electronic device including a semiconductor memory, comprising:
providing a substrate including a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction;
forming source line contacts over the active regions between a pair of word lines;
forming source lines extending in the second direction over the source line contacts;
forming contacts over the active regions disposed between adjacent word lines while belonging to different pairs;
forming variable resistance elements to be coupled to the contacts over the contacts, respectively;
forming bit line contacts to be coupled to the variable resistance elements over the variable resistance element, respectively; and
forming bit lines extending in the first direction and coupled to the bit line contacts.

8. The method of claim 7 , wherein the word lines are formed by forming trenches by selectively etching the substrate and burying lower portions of the trenches with a conductive material.

9. The method of claim 7 , wherein the forming of the contacts is performed such that the contacts penetrate through interlayer dielectrics, wherein the interlayer dielectrics cover the source lines.

10. The method of claim 7 , wherein the forming of the contacts includes forming groups of contacts formed at different heights in the second direction.

11. The method of claim 10 , wherein the forming of the bit lien contacts includes forming groups of bit line contacts which overlap the groups of contacts, respectively, and
upper heights of the groups of bit line contacts are the same.

12. The method of claim 7 , wherein the forming of the variable resistance elements includes forming a material layer including a ferromagnetic material, a ferroelectric material, a phase change material, or a metal oxide and selectively etching the material layer.

Assignees

• Sk Hynix Inc

Inventors

• Moon Joo-Young

Classifications

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title

• H01L45/04

  Electricity · mapped topic

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title