Memory arrays

Patent metadata

Field	Value
Publication number	US-9614007-B2
Application number	US-201514803303-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Jul 20, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

First claim

We claim:

1. A memory array, comprising:
a first memory cell;
a second memory cell directly adjacent to the first memory cell along a lateral direction, and vertically offset relative to the first memory cell;
first and second wordlines over a substrate, the first and second word lines being at a common elevation with the first memory cell being disposed over the first word line and the second memory cell being disposed over the second wordline; and
a bitline extending across the first and second memory cells and being electrically coupled to the first and second memory cells; the first memory cell being in a first vertical stack having a conductive extension material between the first memory cell and the bitline; the second memory cell being in a second vertical stack lacking a conductive extension between the second memory cell and the bitline, the second vertical stack comprising a first electrode material over and spaced from the second wordline, a programmable material over the first electrode material and an upper electrode material over the programmable material and in physical contact with the bitline.

2. The memory array of claim 1 wherein the first and second memory cells change in resistivity in transitioning from one memory state to another.

3. The memory array of claim 1 wherein the first and second memory cells comprise programmable regions containing phase change material.

4. The memory array of claim 3 wherein the phase change material comprises chalcogenide.

5. The memory array of claim 1 wherein:
the first and second memory cells comprise programmable regions; and
the programmable region of the first memory cell vertically overlaps the programmable region of the second memory cell.

6. The memory array of claim 1 wherein:
the first and second memory cells comprise programmable regions; and
the programmable region of the first memory cell does not vertically overlap the programmable region of the second memory cell.

7. The memory array of claim 1 being a deck of a 3D memory configuration.

8. A memory array, comprising: memory cells arranged in a grid having columns and rows; the memory cells having programmable regions, each of the memory cells having an first electrode material, a second electrode material and a third electrode material, the first and second electrode materials being separated by a select device material and the second and third electrode materials being separated by a programmable material, the memory cells comprising a first memory cell and a second memory cell immediately adjacent to one another in a common column of memory cells; wherein the first electrode of the first memory cell is in physical contact with a first wordline and the third electrode of the first memory cell is spaced from a bitline by a conductive extension material; and wherein the first electrode of the second memory cell is spaced from a second wordline by the conductive extension material and the third electrode of the second memory cell is in direct physical contact with the bit line; and wherein the first and second wordlines are at a common elevation.

9. The memory array of claim 8 wherein the programmable regions of memory cells in a common row as one another have a same height as one another.

10. The memory array of claim 8 wherein the programmable regions of memory cells in a common row as one another alternate in height between a first height and a second height which is vertically offset relative to the first height.

11. The memory array of claim 8 wherein the programmable regions alternate in height between a first height and a second height which is vertically offset relative to the first height; and wherein the programmable regions at the first height vertically overlap the programmable regions at the second height.

12. The memory array of claim 8 wherein the programmable regions alternate in height between a first height and a second height which is vertically offset relative to the first height; and wherein the programmable regions at the first height do not vertically overlap the programmable regions at the second height.

13. The memory array of claim 8 wherein the programmable regions comprise phase change material.

14. The memory array of claim 8 being a deck of a 3D memory configuration.

15. A memory array, comprising:
a series of data/sense lines extending along a first direction;
a series of access lines extending along a second direction which intersects the first direction;
memory cells vertically between the access lines and the data/sense lines, the memory cells being arranged in a grid having columns along the first direction and rows along the second direction, the memory cells each having a vertical stack comprising a first electrode material separated from a second electrode material by intervening materials comprising a programmable material and a select device material; and
wherein the memory cells in a common column as one another are arranged in two alternating sets along the first direction; with the sets being a first set having memory cells at a first height and a second set having memory cells at a second height which is vertically offset relative to the first height, the second set having the first electrode material in direct physical contact with a single one of the data/sense lines and having the second electrode material spaced from an overlying access line, and the first set having the first electrode material spaced from a second one of the data/sense lines and the second electrode material in direct physical contact with the overlying access line.

16. The memory array of claim 15 wherein the memory cells in a common row as one another have a same height as one another.

17. The memory array of claim 15 wherein the memory cells in a common row as one another are arranged in the two alternating sets along the second direction.

18. The memory array of claim 15 wherein:
the memory cells of the first set are coupled to the data/sense lines through conductive extensions; and
the memory cells of the second set are coupled to the access lines through conductive extensions.

19. The memory array of claim 15 wherein:
the memory cells are part of vertically-extending stacks comprising programmable material sandwiched between first and second electrodes, and comprising select devices spaced from the programmable material by one of the first and second electrodes;
memory cells of the first set are within vertically-extending stacks having select devices beneath the programmable material; and
memory cells of the second set are within vertically-extending stacks having select devices beneath the programmable material.

20. The memory array of claim 15 wherein:
the memory cells are part of vertically-extending stacks comprising programmable material sandwiched between first and second electrodes, and comprising select devices spaced from the programmable material by one of the first and second electrodes;
memory cells of the first set are within vertically-extending stacks having select devices beneath the programmable material; and
memory cells of the second set are within vertically-extending stacks having select devices above the programmable material.

21. The memory array of claim 15 wherein:
the memory cells are part of vertically-extending stacks comprising programmable material sandwiched between first and second electrodes, and comprising select devices spaced from the programmable material by one of the first and second

Assignees

• Micron Technology Inc

Inventors

• Boniardi Mattia
• Redaelli Andrea

Classifications

• H01L45/141

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L27/2481 Primary

  Electricity · mapped topic