Single-diffusion break structure for fin-type field effect transistors

Patent metadata

Field	Value
Publication number	US-10177151-B1
Application number	US-201715632702-A
Country	US
Kind code	B1
Filing date	Jun 26, 2017
Priority date	Jun 26, 2017
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.

First claim

What is claimed is:

1. A method comprising:
forming sacrificial fins in parallel on a substrate, the sacrificial fins including a middle fin between two adjacent fins, the middle fin being in a location for a dummy gate, and the two adjacent fins being in locations for gate conductors of adjacent complementary transistors;
removing portions of the sacrificial fins by forming asymmetric cuts in the sacrificial fins, the asymmetric cuts having larger gaps between fin portions that are closest to the substrate;
forming trenches in the substrate through the asymmetric cuts, each trench having a first width, a first depth, and a bottom;
forming asymmetric trenches in the substrate by cutting a cavity below each trench, the cavity having a second depth measured from the bottom of the trench and a lateral undercut at the bottom of the trench, wherein the lateral undercut has a second width at the bottom of the trench, the second width being larger than the first width;
filling the asymmetric trenches with an insulator to form a single-diffusion break (SDB);
forming channel regions in the substrate below the two adjacent fins;
forming source/drain regions of complementary transistors in the substrate on opposite sides of the channel regions, the single-diffusion break being between two of the source/drain regions of different ones of the adjacent complementary transistors; and
replacing the sacrificial fins with conductors to form the dummy gate over the single-diffusion break and the gate conductors over the channel regions.

2. The method according to claim 1 , the forming asymmetric trenches in the substrate further comprising:
forming trenches in the sacrificial fins defining an active device region with the sacrificial fins;
depositing a spacer layer in the trenches;
forming a cavity below each of the trenches;
removing the spacer layer; and
depositing an isolation layer so as to fill the trenches and the cavity below each of the trenches, forming the single-diffusion break (SDB).

3. The method according to claim 2 , the forming a cavity below each of the trenches further comprising:
using an isotropic etch process on the bottom of the trench.

4. The method according to claim 2 , the forming a cavity below each of the trenches further comprising:
using an anisotropic etch process on the bottom of the trench to extend the first depth of the trench to a second depth,
oxidizing the trench, and
removing oxidized portions of the substrate, leaving a cavity.

5. The method of claim 2 ,
wherein the cavity has a second depth and a second width, the second width being greater than the first width, and the second depth being greater than the second width.

6. The method of claim 1 ,
wherein the sacrificial fin has a first top surface,
wherein the source/drain regions of the different ones of the adjacent complementary transistors have second top surfaces, and
wherein the method further comprises forming contacts between the first top surface and the second top surfaces.

7. The method according to claim 6 , further comprising:
depositing a conformal dielectric layer on the first top surface and the second top surfaces;
forming metal plug openings through the conformal dielectric layer to the source/drain regions of the adjacent complementary transistors;
forming, in the metal plug openings, metal plugs;
forming a contact opening through the conformal dielectric layer to the gate conductors; and
filling the contact opening with conductive material to form a first contact to a first one of the complementary transistors and a second contact to a second one of the complementary transistors.

8. The method of claim 1 , wherein the complementary transistors comprise a complementary metal oxide semiconductor (CMOS) device with both an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET).

9. A method comprising:
forming a first semiconductor body for a first-type field effect transistor and a second semiconductor body for a second-type field effect transistor in a substrate, the first-type field effect transistor being adjacent to the second-type field effect transistor;
forming, on a first channel region in the first semiconductor body and a second channel region in the second semiconductor body, sacrificial fins in parallel, the sacrificial fins including a middle fin between two adjacent fins, the middle fin being in a location for a dummy gate, and the two adjacent fins being in locations for gate conductors of the first-type field effect transistor and the second-type field effect transistor;
removing portions of the sacrificial fins to form asymmetric cuts in the sacrificial fins, the asymmetric cuts having larger gaps between fin portions that are closest to the substrate;
forming trenches in the substrate through the asymmetric cuts, each trench having a first width, a first depth, and a bottom;
forming asymmetric trenches in the substrate by cutting a cavity below each trench, the cavity having a second depth measured from the bottom of the trench and a lateral undercut at the bottom of the trench, wherein the lateral undercut has a second width at the bottom of the trench, the second width being larger than the first width;
filling the asymmetric trenches with an insulator to form a single-diffusion break;
forming source/drain regions of the first-type field effect transistor and the second-type field effect transistor in the substrate on opposite sides of the first channel region and the second channel region, respectively, the single-diffusion break being between two of the source/drain regions of the transistors; and
replacing the sacrificial fins with conductors to form the dummy gate over the single-diffusion break and the gate conductors over the channel regions.

10. The method according to claim 9 , the forming asymmetric trenches in the substrate further comprising:
forming trenches in the sacrificial fins defining an active device region with the sacrificial fins;
depositing a spacer layer in the trenches;
forming a cavity below each of the trenches;
removing the spacer layer; and
depositing an isolation layer so as to fill the trenches and the cavity below each of the trenches, forming the single-diffusion break (SDB).

11. The method according to claim 10 , the forming a cavity below each of the trenches further comprising:
using an isotropic etch process on the bottom of the trench.

12. The method according to claim 10 , the forming a cavity below each of the trenches further comprising:
using an anisotropic etch process on the bottom of the trench to extend the first depth of the trench to a second depth,
oxidizing the trench, and
removing oxidized portions of the substrate, leaving a cavity.

13. The method of claim 10 ,
wherein the cavity has a second depth and a second width, the second width being greater than the first width, and the second depth being greater than the second width.

14. The method according to claim 9 , further comprising:
depositing a conformal dielectric layer on the first semiconductor body and the second semiconductor body;
forming metal plug openings through the conformal dielectric layer to the source/drain regions of the first-type field effect transistor and the second-type field effect transistor;
forming, in the metal plug openings, metal plugs;
forming a contact opening through the conformal dielectric layer to the gate conductors of the first-type field effect transistor and the second-type field effect transistor; and
filling the contact opening with conductive material to form a first contact to the fi

Assignees

• Globalfoundries Inc

Inventors

• Wang Yanzhen
• Zang Hui
• Liu Bingwu

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L21/823878

  Electricity · mapped topic