Method for forming single diffusion breaks between finFET devices and the resulting devices

Patent metadata

Field	Value
Publication number	US-9406676-B2
Application number	US-201514676165-A
Country	US
Kind code	B2
Filing date	Apr 1, 2015
Priority date	Dec 29, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

First claim

What is claimed is:

1. A method, comprising:
forming a fin in a semiconductor substrate;
forming a plurality of sacrificial gate structures above said fin;
forming an interlayer dielectric layer above said sacrificial gate structures;
planarizing said interlayer dielectric layer to expose said sacrificial gate structures,
forming a hard mask layer above said interlayer dielectric layer and above said sacrificial gate structures;
forming a first opening in said hard mask layer so as to expose a selected one of said sacrificial gate structures;
removing said selected one of said sacrificial gate structures to define a second opening that exposes a portion of said fin;
performing an etch process through said second opening on said exposed portion of said fin to define a first recess in said fin;
forming a dielectric material layer above said hard mask layer so as to fill and first recess and to define a diffusion break in said fin;
planarizing said dielectric material layer using said hard mask layer as a stop layer; and
performing an etch process to remove said hard mask layer after planarizing said dielectric material layer.

2. The method of claim 1 , further comprising:
etching said fin to define second recesses adjacent said sacrificial gate structures prior to removing said selected one of said sacrificial gate structures; and
filling said second recesses with an epitaxial material.

3. The method of claim 1 , further comprising replacing said remaining ones of said plurality of sacrificial gate structures with replacement gate structures.

4. The method of claim 1 , further comprising
forming a mask layer above said hard mask layer;
patterning said mask layer to expose said hard mask layer above said selected one of said sacrificial gate structures; and
etching said hard mask layer using said mask layer as an etch mask to define said first opening.

5. The method of claim 4 , further comprising:
removing said mask layer; and
forming said dielectric material layer in said first recess, in said first opening, and in said second opening to define said diffusion break.

6. The method of claim 1 , further comprising:
forming a cap layer above said interlayer dielectric layer and above said sacrificial gate structures prior to forming said hard mask layer, wherein said hard work mask layer is formed above said cap layer and said first opening extends through said cap layer;
selectively removing a first portion of said dielectric material layer disposed in said first opening after planarizing said dielectric material layer and prior to performing said etch process to remove said hard mask layer; and
removing said cap layer and a second portion of said dielectric material layer disposed in said second opening so as to expose remaining ones of said plurality of sacrificial gate structures.

7. The method of claim 6 , further comprising replacing said remaining ones of said plurality of sacrificial gate structures with replacement gate structures.

8. The method of claim 6 , wherein removing said cap layer and a second portion of said dielectric material layer comprises performing a timed etch process.

9. The method of claim 6 , wherein selectively removing a first portion of said dielectric material layer further comprises performing a selective etch process.

10. The method of claim 9 , wherein said selective etch process comprises a wet etch process.

11. A method, comprising:
forming a fin in a semiconductor substrate;
forming a plurality of sacrificial gate structures above said fin;
forming an interlayer dielectric layer above said sacrificial gate structures;
planarizing said interlayer dielectric layer to expose said sacrificial gate structures;
forming a cap layer above said interlayer dielectric layer and above said sacrificial gate structures;
forming a hard mask layer above said cap layer;
forming a first opening in said hard mask layer and said cap layer so as to expose a selected one of said sacrificial gate structures;
removing said selected one of said sacrificial gate structures to define a second opening that exposes a portion of said fin;
performing an etch process through said second opening on said exposed portion of said fin to define a first recess in said fin;
forming a dielectric material layer above said hard mask layer so as to fill said first recess and said first and second openings and to define a diffusion break in said fin;
planarizing said dielectric material layer using said hard mask layer as a stop layer;
selectively removing a first portion of said dielectric material layer disposed in said first opening after planarizing said dielectric material layer;
performing an etch process to remove said hard mask layer after selectively removing said first portion of said dielectric material layer;
removing said cap layer and a second portion of said dielectric material layer disposed in said second opening so as to expose remaining ones of said plurality of sacrificial gate structures; and
replacing said remaining ones of said plurality of sacrificial gate structures with replacement gate structures.

12. The method of claim 11 , wherein removing said cap layer and a second portion of said dielectric material layer comprises performing a timed etch process.

13. The method of claim 11 , wherein selectively removing a first portion of said dielectric material layer further comprises performing a selective etch process.

14. The method of claim 13 , wherein said selective etch process comprises a wet etch process.

Assignees

• Globalfoundries Inc

Inventors

• Yu Hong
• Shen Hongliang
• Hu Zhenyu
• Liu Jin Ping

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title