Single diffusion break with improved isolation and process window and reduced cost

Patent metadata

Field	Value
Publication number	US-9431396-B2
Application number	US-201514609564-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 30, 2015
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Methods of forming a SDB with a partial or complete insulator structure formed over the SDB and resulting devices are provided. Embodiments include forming a SDB with a first width in a substrate; forming a first metal gate in an ILD on top of the SDB, with a second width larger than the first width; forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate; forming a photoresist over the second and third gates; removing the first metal gate down to the SDB, forming a cavity; removing the photoresist; and filling the cavity with an insulator layer.

First claim

What is claimed is:

1. A method comprising:
forming a single diffusion break (SDB) with a first width in a substrate;
forming a first metal gate in an interlayer dielectric (ILD) on top of the SDB, with a second width larger than the first width;
forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate;
forming a photoresist over the second and third gates;
removing the first metal gate down to the SDB, forming a cavity;
removing the photoresist; and
filling the cavity with an insulator layer,
wherein each of the second and third metal gates is formed to a third width smaller than the second width.

2. The method according to claim 1 , further comprising:
etching each of the first, second, and third metal gates, forming a recess in each, prior to forming the photoresist; and
filling the recess in each of the second and third metal gates with the insulator layer concurrently with filling the cavity.

3. The method according to claim 2 , wherein source/drain (S/D) regions are formed on the substrate at opposite sides of each of the second and third metal gates, the method further comprising forming a self-aligned contact through the ILD down to the source/drain regions.

4. The method according to claim 1 , comprising forming the insulator layer of silicon nitride (SiN).

5. The method according to claim 1 , wherein the insulator layer is formed with a width greater than the first width and each of the third widths is smaller than the width of the insulator layer.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Liu Bingwu

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title