Single diffusion break with improved isolation and process window and reduced cost

Patent metadata

Field	Value
Publication number	US-2016225762-A1
Application number	US-201514609564-A
Country	US
Kind code	A1
Filing date	Jan 30, 2015
Priority date	Jan 30, 2015
Publication date	Aug 4, 2016
Grant date	—

Abstract

Methods of forming a SDB with a partial or complete insulator structure formed over the SDB and resulting devices are provided. Embodiments include forming a SDB with a first width in a substrate; forming a first metal gate in an ILD on top of the SDB, with a second width larger than the first width; forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate; forming a photoresist over the second and third gates; removing the first metal gate down to the SDB, forming a cavity; removing the photoresist; and filling the cavity with an insulator layer.

First claim

1 . A method comprising:
forming a single diffusion break (SDB) with a first width in a substrate; forming a first metal gate in an interlayer dielectric (ILD) on top of the SDB, with a second width larger than the first width; forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate; forming a photoresist over the second and third gates; removing the first metal gate down to the SDB, forming a cavity; removing the photoresist; and filling the cavity with an insulator layer, wherein each of the second and third metal gates is formed to a third width smaller than the second width.

2 . (canceled)

3 . The method according to claim 1 , further comprising:
etching each of the first, second, and third metal gates, forming a recess in each, prior to forming the photoresist; and filling the recess in each of the second and third metal gates with the insulator layer concurrently with filling the cavity.

4 . The method according to claim 3 , wherein source/drain (S/D) regions are formed on the substrate at opposite sides of each of the second and third metal gates, the method further comprising forming a self-aligned contact through the ILD down to the source/drain regions.

5 . The method according to claim 1 , comprising forming the insulator layer of silicon nitride (SiN).

6 . A device comprising:
a single diffusion break (SDB) having a first width formed in a substrate; first and second metal gates, each with spacers at opposite sides thereof, formed on the substrate on opposite sides of the SDB, the first and second metal gates laterally separated from the SDB; an interlayer dielectric (ILD) between the first and second metal gates, the ILD having a cavity with a second width larger than the first width above and down to the SDB; an insulator layer formed in the cavity; and source/drain (S/D) regions formed on the substrate on opposite sides of each of the first and second metal gates.

7 . The device according to claim 6 , wherein the first and second metal gates each have a third width smaller than the second width.

8 . The device according to claim 6 , wherein the insulator layer is formed of silicon nitride (SiN).

9 . The device according to claim 6 , further comprising a self-aligned contact being formed through the ILD down to the S/D regions.

10 . A method comprising:
forming a single diffusion break (SDB) with a first width in a substrate; forming a polysilicon (poly) layer over the substrate; etching a recess in the poly layer over the SDB, the recess having a second width greater than the first width; forming a nitride layer over the poly layer and filling the recess; etching the poly layer forming first and second poly gates at opposite sides of and laterally separated from the SDB and forming a structure over the SDB having the second width and including the nitride layer filled recess; forming an interlayer dielectric (ILD) around the first and second poly gates and around the structure; and replacing the first and second poly gates with first and second metal gates, respectively.

11 . The method according to claim 10 , comprising forming the recess in the poly layer by:
forming a photoresist layer on the poly layer, the photoresist layer having an opening above the SDB; enlarging the opening to the second width; and etching the poly layer through the enlarged opening.

12 . The method according to claim 10 , comprising etching the recess in the poly layer to a depth of 10 nm to 200 nm.

13 . The method according to claim 10 , comprising forming each of the first and second poly gates to a third width less than the second width.

14 . The method according to claim 10 , further comprising forming a self-aligned contact (SAC) through the ILD down to the source/drain regions.

15 . The method according to claim 14 , further comprising recessing each of the first and second metal gates and the nitride layer and filling the recesses with a second nitride prior to forming the SAC.

16 . A device comprising:
a single diffusion break (SDB) with a first width formed in a substrate; a structure over the SDB, with a second width larger than the first width; first and second metal gates formed on opposite sides of the structure, the first and second metal gates each having a third width smaller than the second width and being laterally separated from the insulator structure; source/drain (S/D) regions formed on the substrate on opposite sides of each of the first and second metal gates; an interlayer dielectric (ILD) around the first and second metal gates and around the structure and over the S/D regions, wherein the structure comprises a nitride layer.

17 . The device according to claim 16 , wherein the structure comprises poly silicon under the nitride layer.

18 . The device according to claim 17 , wherein the first and second metal gates each include a nitride cap, the device further including a self-aligned contact (SAC) formed through the ILD down to the source/drain regions.

19 . The device according to claim 16 , wherein the structure consists of the nitride layer.

20 . The device according to claim 19 , wherein the first and second metal gates each include a nitride cap, the device further including a self-aligned contact (SAC) formed through the ILD down to the source/drain regions.

21 . The method according to claim 1 , wherein the insulator layer is formed with a width greater than the first width and each of the third widths is smaller than the width of the insulator layer.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Liu Bingwu

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title