Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device

Patent metadata

Field	Value
Publication number	US-9524911-B1
Application number	US-201514858412-A
Country	US
Kind code	B1
Filing date	Sep 18, 2015
Priority date	Sep 18, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Methods for creating self-aligned FINFET SDBs for minimum gate junction pitch and epitaxy formation. Embodiments include forming separated openings in a hard mask on upper surfaces of Si fins; forming cavities in the fins, each of the cavities having a concave shape and a width extending under the hard mask on each side of the cavity; forming trenches in the fins, the trenches having an upper width substantially equal to a width of the openings and less than the width of a cavity; removing the hard mask; filling the trenches and the cavities with oxide, forming STI regions; forming an oxide mask layer on the upper surfaces of the fins and the STI regions; removing upper portions of the oxide in sections between the STI regions; and removing remaining portions of the oxide mask revealing the fins and upper surfaces of the STI regions.

First claim

What is claimed is:

1. A method comprising:
forming separated openings in a hard mask layer on upper surfaces of silicon (Si) fins;
forming cavities in the Si fins through the openings, each of the cavities having a concave shape and a width extending under the hard mask layer on each side of the cavity;
forming trenches in the Si fins through the openings and the cavities, each of the trenches having an upper width equal to a width of the openings and less than the width of a cavity;
removing the hard mask layer;
filling the trenches and the cavities with an oxide layer, forming shallow trench isolation (STI) regions;
forming an oxide mask layer on the upper surface of the Si fins and upper surfaces of the STI regions;
removing upper portions of the oxide mask layer in sections between the STI regions; and
removing remaining portions of the oxide mask layer revealing the Si fins and upper surfaces of the STI regions.

2. The method according to claim 1 , comprising forming the cavities by an isotropic etching process.

3. The method according to claim 1 , comprising forming the trenches by an anisotropic etching process.

4. The method according to claim 1 , wherein the STI regions include self-aligned and concave shaped upper portions.

5. The method according to claim 4 , further comprising:
forming a pair of source/drain (S/D) regions in the Si fin in between adjacent STI regions, wherein upper surfaces of the S/D regions adjacent to the STI regions are lower than the concave shaped upper portions of the STI regions.

6. The method according to claim 5 , wherein forming the S/D regions comprises:
forming a gate electrode centered between a pair of adjacent STI regions;
forming a cavity in the Si fin on opposite sides of the gate electrode;
depositing a Si seed layer on a sidewall of the cavity adjacent to the concave shaped upper portions; and
epitaxially growing S/D materials in the cavity.

7. The method according to claim 5 , wherein the STI regions extend deeper than the S/D regions.

8. The method according to claim 1 , comprises forming the hard mask layer of an amorphous carbon, an organic dielectric, or a silicon nitride material.

9. The method according to claim 1 , comprises forming the separated openings in the hard mask through a fin-cut lithography mask.

10. The method according to claim 1 , comprises removing the upper portions of the oxide mask layer through a reverse fin-cut lithography mask.

11. A method comprising:
forming separated openings in a hard mask layer on upper surfaces of silicon (Si) fins;
forming cavities in the Si fins through the openings, by an isotropic etching process, each of the cavities having a concave shape and a width extending under the hard mask layer on each side of the cavity;
forming trenches in the Si fins through the openings and the cavities, by an anisotropic etching process, each of the trenches having an upper width equal to a width of the openings and less than the width of a cavity;
removing the hard mask layer;
filling the trenches and the cavities with an oxide layer, forming shallow trench isolation (STI) regions;
forming an oxide mask layer on the upper surface of the Si fins and upper surfaces of the STI regions;
removing upper portions of the oxide mask layer in sections between the STI regions; and
removing remaining portions of the oxide mask layer revealing the Si fins and upper surfaces of the STI regions, wherein the STI regions include self-aligned and concave shaped upper portions.

12. The method according to claim 11 , further comprising:
forming a pair of source/drain (S/D) regions in the Si fin in between adjacent STI regions, wherein upper surfaces of the S/D regions adjacent to the STI regions are lower than the concave shaped upper portions of the STI regions, and wherein the STI regions extend deeper than the S/D regions.

13. The method according to claim 12 , wherein forming the S/D regions comprises:
forming a gate electrode centered between a pair of adjacent STI regions;
forming a cavity in the Si fin on opposite sides of the gate electrode;
depositing a Si seed layer on a sidewall of the cavity adjacent to the concave shaped upper portions; and
epitaxially growing S/D materials in the cavity.

14. The method according to claim 11 , comprises forming the hard mask layer of an amorphous carbon, an organic dielectric, or a silicon nitride material.

15. The method according to claim 11 , comprises forming the separated openings in the hard mask through a fin-cut lithography mask.

16. The method according to claim 11 , comprises removing the upper portions of the oxide mask layer through a reverse fin-cut lithography mask.

Assignees

• Globalfoundries Inc

Inventors

• Tsai Hao-Cheng
• Lee Yong Meng
• Chi Min-Hwa

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title