Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10043918-B2
Application number	US-201715645217-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Jul 8, 2011
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a first non-single crystal oxide semiconductor layer over and in contact with the gate insulating film, the first non-single crystal oxide semiconductor layer comprising indium and zinc;
a second non-single crystal oxide semiconductor layer over and in contact with the first non-single crystal oxide semiconductor layer, the second non-single crystal oxide semiconductor layer comprising indium, zinc and gallium;
a drain electrode layer over and in contact with the second non-single crystal oxide semiconductor layer;
a source electrode layer over and in contact with the second non-single crystal oxide semiconductor layer; and
an oxide insulating film over the drain electrode layer and the source electrode layer, wherein the oxide insulating film contacts the second non-single crystal oxide semiconductor layer at least in a region between the drain electrode layer and the source electrode layer,
wherein a proportion of gallium with respect to indium in the second non-single crystal oxide semiconductor layer is greater than a proportion of gallium with respect to indium in the first non-single crystal oxide semiconductor layer, and
wherein at least an upper portion of the second non-single crystal oxide semiconductor layer comprises a crystal, a c-axis of the crystal being perpendicular to an upper surface of the second non-single crystal oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein an energy gap of the first non-single crystal oxide semiconductor layer is smaller than an energy gap of the second non-single crystal oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the first non-single crystal oxide semiconductor layer further comprises Sn.

4. The semiconductor device according to claim 1 , wherein the second non-single crystal oxide semiconductor layer covers a top and side surfaces of the first non-single crystal oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the first non-single crystal oxide semiconductor layer and the second non-single crystal oxide semiconductor layer each includes a low-resistance region including a dopant.

6. The semiconductor device according to claim 5 , wherein the low-resistance region is adjacent to a channel formation region.

7. The semiconductor device according to claim 1 , wherein each of the drain electrode layer and the source electrode layer comprises Cu.

8. A semiconductor device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a first non-single crystal oxide semiconductor layer over and in contact with the gate insulating film, the first non-single crystal oxide semiconductor layer comprising indium and zinc;
a second non-single crystal oxide semiconductor layer over and in contact with the first non-single crystal oxide semiconductor layer, the second non-single crystal oxide semiconductor layer comprising indium, zinc and gallium;
a drain electrode layer over and in contact with the second non-single crystal oxide semiconductor layer;
a source electrode layer over and in contact with the second non-single crystal oxide semiconductor layer; and
an oxide insulating film over the drain electrode layer and the source electrode layer, wherein the oxide insulating film contacts the second non-single crystal oxide semiconductor layer at least in a region between the drain electrode layer and the source electrode layer,
wherein an energy gap of the first non-single crystal oxide semiconductor layer is smaller than an energy gap of the second non-single crystal oxide semiconductor layer, and
wherein at least an upper portion of the second non-single crystal oxide semiconductor layer comprises a crystal, a c-axis of the crystal being perpendicular to an upper surface of the second non-single crystal oxide semiconductor layer.

9. The semiconductor device according to claim 8 , wherein the second non-single crystal oxide semiconductor layer covers a top and side surfaces of the first non-single crystal oxide semiconductor layer.

10. The semiconductor device according to claim 8 , wherein the second non-single crystal oxide semiconductor layer includes a low-resistance region including a dopant.

11. The semiconductor device according to claim 10 , wherein the low-resistance region is adjacent to a channel formation region.

12. The semiconductor device according to claim 8 , wherein each of the drain electrode layer and the source electrode layer comprises Cu.

13. A semiconductor device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a non-single crystal oxide semiconductor film over and in contact with the gate insulating film;
a drain electrode layer over and in contact with the non-single crystal oxide semiconductor film;
a source electrode layer over and in contact with the non-single crystal oxide semiconductor film; and
an oxide insulating film over the drain electrode layer and the source electrode layer, wherein the oxide insulating film contacts the non-single crystal oxide semiconductor film at least in a region between the drain electrode layer and the source electrode layer,
wherein the non-single crystal oxide semiconductor film comprises a first region in contact with an upper surface of the gate insulating film and a second region, above the first region, comprising an upper surface of the non-single crystal oxide semiconductor film,
wherein a proportion of gallium with respect to indium in the second region is greater than a proportion of gallium with respect to indium in the first region, and
wherein the second region comprises a crystal, a c-axis of the crystal being perpendicular to the upper surface of the non-single crystal oxide semiconductor film.

14. The semiconductor device according to claim 13 , wherein an energy gap of the first region is smaller than an energy gap of the second region.

15. The semiconductor device according to claim 13 , wherein the non-single crystal oxide semiconductor film includes a low-resistance region including a dopant.

16. The semiconductor device according to claim 15 , wherein the low-resistance region is adjacent to a channel formation region.

17. The semiconductor device according to claim 13 , wherein each of the drain electrode layer and the source electrode layer comprises Cu.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Shinohara Satoshi

Classifications

• H10B41/70

  the floating gate being an electrode shared by two or more components · CPC title

• H10D86/425

  having different crystal properties in different TFTs or within an individual TFT · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title