Semiconductor device, display device, and electronic appliance

Patent metadata

Field	Value
Publication number	US-9406808-B2
Application number	US-201213671638-A
Country	US
Kind code	B2
Filing date	Nov 8, 2012
Priority date	Oct 8, 2009
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first transistor comprising:
a first oxide semiconductor layer comprising indium, the first oxide semiconductor layer including a first region, a second region and a first channel formation region between the first region and the second region;
a first oxide insulating layer over and in contact with the first channel formation region;
a first metal layer over the first region and the first oxide insulating layer, the first metal layer being in contact with the first region and a top surface of the first oxide insulating layer;
a second metal layer over the second region and the first oxide insulating layer, the second metal layer being in contact with the second region and the top surface of the first oxide insulating layer; and
a gate electrode under the first channel formation region with a gate insulating layer therebetween; and

a second transistor comprising:
a second oxide semiconductor layer including a second channel formation region; and
a second oxide insulating layer over and in contact with the second channel formation region,

wherein the second oxide semiconductor layer further includes a third region,
wherein a thickness of the third region is smaller than a thickness of the second channel formation region,
wherein the first oxide semiconductor layer comprises a nanocrystal,
wherein the first channel formation region is i-type,
wherein the first region has an n-type conductivity, and
wherein the second region has an n-type conductivity.

2. The semiconductor device according to claim 1 , wherein size of the nanocrystal is greater than or equal to 1 nm and less than or equal to 20 nm.

3. The semiconductor device according to claim 1 , wherein the first metal layer and the second metal layer comprise titanium.

4. The semiconductor device according to claim 1 , wherein the gate electrode is located below the first oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the first oxide insulating layer comprises silicon and oxygen.

6. A semiconductor device comprising:
a first transistor comprising:
a first oxide semiconductor layer comprising indium, the first oxide semiconductor layer including a first region, a second region and a first channel formation region between the first region and the second region;
a first oxide insulating layer over and in contact with the first channel formation region;
a first metal layer over the first region and the first oxide insulating layer, the first metal layer being in contact with the first region;
a second metal layer over the second region and the first oxide insulating layer, the second metal layer being in contact with the second region; and
a gate electrode adjacent to the first channel formation region with a gate insulating layer therebetween; and

a second transistor comprising:
a second oxide semiconductor layer including a second channel formation region; and
a second oxide insulating layer over and in contact with the second channel formation region,

wherein the second oxide semiconductor layer further includes a third region,
wherein a thickness of the third region is smaller than a thickness of the second channel formation region,
wherein an oxygen concentration of the first channel formation region is higher than an oxygen concentration of the first region,
wherein the oxygen concentration of the first channel formation region is higher than an oxygen concentration of the second region,
wherein the first channel formation region is i-type,
wherein the first region has an n-type conductivity, and
wherein the second region has an n-type conductivity.

7. The semiconductor device according to claim 6 , wherein the first oxide semiconductor layer comprises crystals which are c-axis oriented in a direction perpendicular to a surface of the first oxide semiconductor layer.

8. The semiconductor device according to claim 6 , wherein the first oxide semiconductor layer comprises crystals.

9. The semiconductor device according to claim 6 , wherein the first metal layer and the second metal layer comprise titanium.

10. The semiconductor device according to claim 6 , wherein the gate electrode is located below the first oxide semiconductor layer.

11. The semiconductor device according to claim 6 , wherein the first oxide insulating layer comprises silicon and oxygen.

12. The semiconductor device according to claim 6 , wherein the first oxide semiconductor layer comprises nanocrystals.

13. A semiconductor device comprising:
a first transistor comprising:
a first oxide semiconductor layer comprising indium, the first oxide semiconductor layer including a first region, a second region and a first channel formation region between the first region and the second region;
a first oxide insulating layer over and in contact with the first channel formation region;
a first metal layer over the first region and the first oxide insulating layer, the first metal layer being in contact with the first region;
a second metal layer over the second region and the first oxide insulating layer, the second metal layer being in contact with the second region; and
a gate electrode adjacent to the first channel formation region with a gate insulating layer therebetween; and

a second transistor comprising:
a second oxide semiconductor layer including a second channel formation region; and
a second oxide insulating layer over and in contact with the second channel formation region,

wherein the second oxide semiconductor layer further includes a third region,
wherein a thickness of the third region is smaller than a thickness of the second channel formation region,
wherein the first channel formation region is i-type,
wherein the first region has an n-type conductivity, and
wherein the second region has an n-type conductivity.

14. The semiconductor device according to claim 13 , wherein the first oxide semiconductor layer comprises crystals which are c-axis oriented in a direction perpendicular to a surface of the first oxide semiconductor layer.

15. The semiconductor device according to claim 13 , wherein the first oxide semiconductor layer comprises crystals.

16. The semiconductor device according to claim 13 , wherein the first metal layer and the second metal layer comprise titanium.

17. The semiconductor device according to claim 13 , wherein the gate electrode is located below the first oxide semiconductor layer.

18. The semiconductor device according to claim 13 , wherein the first oxide insulating layer comprises silicon and oxygen.

19. The semiconductor device according to claim 13 , wherein the first oxide semiconductor layer comprises nanocrystals.

20. A semiconductor device comprising:
a first transistor comprising:
a first oxide semiconductor layer comprising indium, the first oxide semiconductor layer including a first region, a second region and a first channel formation region between the first region and the second region;
a first oxide insulating layer over and in contact with the first channel formation region;
a first metal layer over the first region and the first oxide insulating layer, the first metal layer being in contact with the first region;
a second metal layer over the second region and the first oxide insulating layer, the second metal layer being in contact with the second region; and
a gate electrode adjacent to the first channel formation region with a gate insulating layer; and

a sec

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Sakakura Masayuki
• Watanabe Ryosuke
• Sakata Junichiro
• Akimoto Kengo
• Miyanaga Akiharu
• Hirohashi Takuya
• Kishida Hideyuki

Classifications

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title