Semiconductor device, display device, and electronic appliance

Patent metadata

Field	Value
Publication number	US-2016336456-A1
Application number	US-201615220532-A
Country	US
Kind code	A1
Filing date	Jul 27, 2016
Priority date	Oct 8, 2009
Publication date	Nov 17, 2016
Grant date	—

Abstract

In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a gate electrode layer; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising:
a first region;
a second region;
a third region between the first region and the second region;
a fourth region between the first region and the third region; and
a fifth region between the second region and the third region;
a first insulating layer over the oxide semiconductor layer, the first insulating layer comprising oxygen; a source electrode layer over the oxide semiconductor layer; and a drain electrode layer over the oxide semiconductor layer, wherein the first region is in contact with the source electrode layer, wherein the second region is in contact with the drain electrode layer, wherein the third region is in contact with the first insulating layer, wherein the fourth region has a thickness less than the third region, wherein the fifth region has a thickness less than the third region, and wherein the oxide semiconductor layer comprises a nanocrystal.

3 . The semiconductor device according to claim 2 ,
wherein the source electrode layer and the drain electrode layer comprise titanium.

4 . The semiconductor device according to claim 2 ,
wherein the first insulating layer further comprises silicon.

5 . The semiconductor device according to claim 2 ,
wherein the oxide semiconductor layer comprises indium.

6 . The semiconductor device according to claim 2 ,
wherein the thickness of the fourth region is less than the first region and the second region, and wherein the thickness of the fifth region is less than the first region and the second region.

7 . The semiconductor device according to claim 2 , further comprising a second insulating layer over the oxide semiconductor layer, the first insulating layer, the source electrode layer and the drain electrode layer,
wherein the second insulating layer is in contact with the fourth region of the oxide semiconductor layer and the fifth region of the oxide semiconductor layer.

8 . The semiconductor device according to claim 7 ,
wherein the second insulating layer comprises oxygen.

9 . A semiconductor device comprising:
a gate electrode layer; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising:
a first region;
a second region;
a third region between the first region and the second region;
a fourth region between the first region and the third region; and
a fifth region between the second region and the third region;
a first insulating layer over the oxide semiconductor layer, the first insulating layer comprising oxygen; a source electrode layer over the oxide semiconductor layer; and a drain electrode layer over the oxide semiconductor layer, wherein the first region is in contact with the source electrode layer, wherein the second region is in contact with the drain electrode layer, wherein the third region is in contact with the first insulating layer, wherein the fourth region has a thickness less than the third region, wherein the fifth region has a thickness less than the third region, wherein the oxide semiconductor layer comprises a crystal, and wherein a size of the crystal is greater than or equal to 1 nm and less than or equal to 20 nm.

10 . The semiconductor device according to claim 9 ,
wherein the source electrode layer and the drain electrode layer comprise titanium.

11 . The semiconductor device according to claim 9 ,
wherein the first insulating layer further comprises silicon.

12 . The semiconductor device according to claim 9 ,
wherein the oxide semiconductor layer comprises indium.

13 . The semiconductor device according to claim 9 ,
wherein the thickness of the fourth region is less than the first region and the second region, and wherein the thickness of the fifth region is less than the first region and the second region.

14 . The semiconductor device according to claim 9 , further comprising a second insulating layer over the oxide semiconductor layer, the first insulating layer, the source electrode layer and the drain electrode layer,
wherein the second insulating layer is in contact with the fourth region of the oxide semiconductor layer and the fifth region of the oxide semiconductor layer.

15 . The semiconductor device according to claim 14 ,
wherein the second insulating layer comprises oxygen.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Sakakura Masayuki
• Watanabe Ryosuke
• Sakata Junichiro
• Akimoto Kengo
• Miyanaga Akiharu
• Hirohashi Takuya
• Kishida Hideyuki

Classifications

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title