Semiconductor device, electronic component, and electronic device

Patent metadata

Field	Value
Publication number	US-10037294-B2
Application number	US-201715590406-A
Country	US
Kind code	B2
Filing date	May 9, 2017
Priority date	May 20, 2016
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a processor core;
a memory section; and
a bus,
wherein a signal and data are transmitted between the processor core and the memory section via the bus,
wherein the memory section comprises a first memory,
wherein the first memory comprises first to Moth local arrays,
wherein M 0 is an integer of more than 1,
wherein a jth local array comprises a jth sense amplifier array and a jth local cell array,
wherein j is an integer of 1 to M 0 ,
the jth local cell array is provided over the jth sense amplifier array,
wherein the jth local cell array comprises first to (M 1 ×N)th bit line pairs and a plurality of memory cells,
wherein M 1 and N are each an integer of 1 or more,
wherein one of the plurality of memory cells is electrically connected to any one bit line of the first to (M 1 ×N)th bit line pairs,
wherein each of the plurality of memory cells comprises a capacitor and a transistor,
wherein the transistor controls charging and discharging of the capacitor,
wherein the jth sense amplifier array comprises first to (M 1 ×N)th sense amplifiers,
wherein a hth bit line pair is electrically connected to an hth sense amplifier,
wherein h is an integer of 1 to M 1 ×N,
wherein the first memory is configured to generate a wait signal when the first memory receives a request for writing data to the jth local array over two successive clock cycles from the processor core, and
wherein the processor core is configured to stand by for a request for the memory section on the basis of the wait signal.

2. The semiconductor device according to claim 1 , wherein the first memory is configured to drive the first to M 0 th local arrays on the basis of the wait signal.

3. The semiconductor device according to claim 1 ,
wherein the number of the plurality of memory cells for each bit line in the jth local cell array is 2 x , and
wherein x is an integer of 2 to 7.

4. The semiconductor device according to claim 1 , wherein a channel formation region of the transistor comprises an oxide semiconductor.

5. The semiconductor device according to claim 1 ,
wherein the first memory comprises first to M 1 th global bit line pairs, first to M 1 th global sense amplifiers, and a multiplexer,
wherein an ith global bit line pair is electrically connected to an ith global sense amplifier,
wherein i is an integer of 1 to M 1 , and
wherein the multiplexer is configured to select M 1 bit line pairs from the first to (M 1 ×N)th bit line pairs and to establish electrical continuity between the selected M 1 bit line pairs and the first to M 1 th global bit line pairs.

6. The semiconductor device according to claim 5 , wherein the first to M 1 th global bit line pairs are provided over the first to M 0 th local arrays.

7. The semiconductor device according to claim 1 , wherein the memory section comprises at least one of an SRAM, a flash memory, an ferroelectric RAM, a magnetoresistive RAM, a resistance RAM, and a phase change RAM.

8. An electronic component comprising:
a chip; and
a lead,
wherein the lead is electrically connected to the chip, and
wherein the semiconductor device according to claim 1 is provided in the chip.

9. An electronic device comprising:
the electronic component according to claim 8 ; and
at least one of a display portion, a touch sensor, a microphone, a speaker, an operation key, and a housing.

10. A semiconductor device comprising:
a processor core;
a memory section; and
a bus,
wherein a signal and data are transmitted between the processor core and the memory section via the bus,
wherein the memory section comprises a first memory,
wherein the first memory comprises first to Moth local arrays,
wherein M 0 is an integer of more than 1,
wherein a jth local array comprises a jth sense amplifier array and a jth local cell array,
wherein j is an integer of 1 to M 0 ,
the jth local cell array is provided over the jth sense amplifier array,
wherein the jth local cell array comprises first to (M 1 ×N)th bit line pairs and a plurality of memory cells,
wherein M 1 and N are each an integer of 1 or more,
wherein the plurality of memory cells comprise a first memory cell and a second memory cell,
wherein the first memory cell and the second memory cell are electrically connected to the jth sense amplifier array through one of the first to (M 1 ×N)th bit line pairs,
wherein each of the plurality of memory cells comprises a capacitor and a transistor,
wherein the transistor controls charging and discharging of the capacitor,
wherein the jth sense amplifier array comprises first to (M 1 ×N)th sense amplifiers,
wherein a hth bit line pair is electrically connected to an hth sense amplifier,
wherein h is an integer of 1 to M 1 ×N,
wherein the first memory is configured to generate a wait signal when the first memory receives a request for writing data to the jth local array over two successive clock cycles from the processor core, and
wherein the processor core is configured to stand by for a request for the memory section on the basis of the wait signal.

11. The semiconductor device according to claim 10 , wherein the first memory is configured to drive the first to M 0 th local arrays on the basis of the wait signal.

12. The semiconductor device according to claim 10 ,
wherein the number of the plurality of memory cells for each bit line in the jth local cell array is 2 x , and
wherein x is an integer of 2 to 7.

13. The semiconductor device according to claim 10 , wherein a channel formation region of the transistor comprises an oxide semiconductor.

14. The semiconductor device according to claim 10 ,
wherein the first memory comprises first to M 1 th global bit line pairs, first to M 1 th global sense amplifiers, and a multiplexer,
wherein an ith global bit line pair is electrically connected to an ith global sense amplifier,
wherein i is an integer of 1 to M 1 , and
wherein the multiplexer is configured to select M 1 bit line pairs from the first to (M 1 ×N)th bit line pairs and to establish electrical continuity between the selected M 1 bit line pairs and the first to M 1 th global bit line pairs.

15. The semiconductor device according to claim 14 , wherein the first to M 1 th global bit line pairs are provided over the first to M 0 th local arrays.

16. The semiconductor device according to claim 10 , wherein the memory section comprises at least one of an SRAM, a flash memory, an ferroelectric RAM, a magnetoresistive RAM, a resistance RAM, and a phase change RAM.

17. An electronic component comprising:
a chip; and
a lead,
wherein the lead is electrically connected to the chip, and
wherein the semiconductor device according to claim 10 is provided in the chip.

18. An electronic device comprising:
the electronic component according to claim 17 ; and
at least one of a display portion, a touch sensor, a microphone, a speaker, an operation key, and a housing.

Assignees

• Semiconductor Energy Lab

Inventors

• Onuki tatsuya
• Uesugi Wataru

Classifications

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G11C14/0072

  and the nonvolatile element is a ferroelectric element · CPC title

• G11C15/04

  using semiconductor elements · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title

• G06F13/4256

  using a clocked protocol · CPC title