Memory device and semiconductor device

Patent metadata

Field	Value
Publication number	US-9478276-B2
Application number	US-201514679111-A
Country	US
Kind code	B2
Filing date	Apr 6, 2015
Priority date	Apr 10, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.

First claim

The invention claimed is:

1. A memory device comprising:
a sense amplifier in a first layer; and
a first circuit and a second circuit in a second layer over the first layer,
wherein:
the sense amplifier is electrically connected to a first wiring and a second wiring,
the first circuit comprises a first switch and a first capacitor,
the first switch is configured to be turned on and off in accordance with a potential of a third wiring,
the first capacitor is electrically connected to the first wiring via the first switch,

the second circuit comprises a second switch and a second capacitor,
the second switch is configured to be turned on and off in accordance with a potential of a fourth wiring,
the second capacitor is electrically connected to the second wiring via the second switch,

the first wiring intersects the third wiring in the second layer,
the second wiring intersects the fourth wiring in the second layer,
the first wiring does not intersect the fourth wiring, and
the second wiring does not intersect the third wiring.

2. The memory device according to claim 1 ,
wherein each of the first switch and the second switch comprises a transistor, and
wherein the transistor comprises an oxide semiconductor film which includes a channel formation region.

3. The memory device according to claim 2 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

4. A semiconductor device comprising the memory device according to claim 1 and a logic circuit.

5. A memory device comprising:
a first layer including a sense amplifier;
a first wiring and a second wiring electrically connected to the sense amplifier; and
a second layer over the first layer, the second layer including a third wiring, a fourth wiring, a first region, and a second region,
wherein:
the first region and the second region overlap the sense amplifier,
the first region comprises a plurality of first memory cells,
each of the plurality of first memory cells comprises a first transistor, and is electrically connected to the first wiring and the third wiring,

the second region comprises a plurality of second memory cells,
each of the plurality of second memory cells comprises a second transistor, and is electrically connected to the second wiring and the fourth wiring,

the first wiring intersects the third wiring,
the second wiring intersects the fourth wiring,
the first wiring does not intersect the fourth wiring, and
the second wiring does not intersect the third wiring.

6. The memory device according to claim 5 , wherein each of the first transistor and the second transistor comprises an oxide semiconductor film which includes a channel formation region.

7. The memory device according to claim 6 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

8. A semiconductor device comprising the memory device according to claim 5 and a logic circuit.

9. A memory device comprising:
a first layer including a first sense amplifier and a second sense amplifier;
a first wiring and a second wiring electrically connected to the first sense amplifier;
a third wiring and a fourth wiring electrically connected to the second sense amplifier; and
a second layer over the first layer, the second layer including a fifth wiring, a sixth wiring, a first region, a second region, a third region, and a fourth region,
wherein:
the first region and the third region overlap the first sense amplifier,
the second region and the fourth region overlap the second sense amplifier,
the first region comprises a plurality of first memory cells,
each of the plurality of first memory cells comprises a first transistor, and is electrically connected to the first wiring and the fifth wiring,

the second region comprises a plurality of second memory cells,
each of the plurality of second memory cells comprises a second transistor, and is electrically connected to the second wiring and the sixth wiring,

the third region comprises a plurality of third memory cells,
each of the plurality of third memory cells comprises a third transistor, and is electrically connected to the third wiring and the fifth wiring,

the fourth region comprises a plurality of fourth memory cells,
each of the plurality of fourth memory cells comprises a fourth transistor, and is electrically connected to the fourth wiring and the sixth wiring,

each of the first wiring and the third wiring intersects the fifth wiring,
each of the second wiring and the fourth wiring intersects the sixth wiring,
the first wiring and the third wiring do not intersect the sixth wiring, and
the second wiring and the fourth wiring do not intersect the fifth wiring.

10. The memory device according to claim 9 , wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor film which includes a channel formation region.

11. The memory device according to claim 10 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

12. A semiconductor device comprising the memory device according to claim 9 and a logic circuit.

13. A memory device comprising:
a sense amplifier;
a first circuit and a second circuit each overlapping with the sense amplifier; and
a first wiring, a second wiring, a third wiring, and a fourth wiring, wherein:
the sense amplifier is electrically connected to the first wiring and the second wiring,
the first circuit comprises a first switch electrically connected to the third wiring and a first capacitor electrically connected to the first wiring via the first switch,
the second circuit comprises a second switch electrically connected to the fourth wiring and a second capacitor electrically connected to the second wiring via the second switch,
the first wiring intersects the third wiring, and does not intersect the fourth wiring, and
the second wiring intersects the fourth wiring, and does not intersect the third wiring.

14. The memory device according to claim 13 ,
wherein each of the first switch and the second switch comprises a transistor, and
wherein the transistor comprises an oxide semiconductor film which includes a channel formation region.

15. The memory device according to claim 14 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

16. A semiconductor device comprising the memory device according to claim 13 and a logic circuit.

Assignees

• Semiconductor Energy Lab

Inventors

• Onuki tatsuya

Classifications

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title