Semiconductor memory device and method for driving the same

Patent metadata

Field	Value
Publication number	US-9230615-B2
Application number	US-201213655077-A
Country	US
Kind code	B2
Filing date	Oct 18, 2012
Priority date	Oct 24, 2011
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit line through a first selection transistor, which is a first switch. Since the potential of the second bit line is the inverse of the potential of the first bit line, the potential difference between the first bit line and the second bit line is increased. The increased potential difference is amplified by a known sense amplifier, a flip-flop circuit composed of the first inverter and a second inverter (constituted by an n-channel transistor and a p-channel transistor), or the like.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first bit line;
a second bit line;
a memory cell connected to one of the first bit line and the second bit line;
a first inverter;
a first switch;
a second inverter; and
a second switch,
wherein the first inverter is connected to the first switch,
wherein the second inverter is connected to the second switch,
wherein the first bit line is connected to the first inverter,
wherein the second bit line is connected to the first switch,
wherein the first bit line is connected to the second switch,
wherein the second bit line is connected to the second inverter,
wherein the semiconductor device is configured to take a state that the first switch is on and the second switch is off, and
wherein the semiconductor device is configured that, after the first switch is turned on, the second switch is turned on so that a loop of the first inverter, the first switch, the second inverter, and the second switch is formed.

2. The semiconductor memory device according to claim 1 , wherein a transistor in the memory cell and a transistor in the first inverter are provided in different layers.

3. The semiconductor memory device according to claim 1 , wherein the first switch comprises a plurality of transistors.

4. The semiconductor memory device according to claim 1 , wherein the first switch comprises transistors with different conductivity types.

5. The semiconductor memory device according to claim 1 ,
wherein a channel area of an n-channel transistor included in the first inverter is from 80% to 125% of a channel area of a p-channel transistor included in the first inverter, and
wherein a value obtained by dividing a channel width by a channel length of the p-channel transistor is 2.5 times to 4 times as large as a value obtained by dividing a channel width by a channel length of the n-channel transistor.

6. The semiconductor memory device according to claim 1 , wherein a channel area of an n-channel transistor included in the first inverter is 10 F 2 or larger, where F is the feature size.

7. A semiconductor memory device comprising:
a first bit line;
a second bit line;
a memory cell connected to one of the first bit line and the second bit line;
a first inverter;
a second inverter;
a first switch;
a second switch;
a first power supply line connected to the first inverter;
a second power supply line connected to the first inverter;
a third power supply line connected to the second inverter;
a fourth power supply line connected to the second inverter, and
wherein the first inverter is connected to the first bit line and connected to the second bit line via the first switch,
wherein the second inverter is connected to the second bit line and connected to the first bit line via the second switch,
wherein the semiconductor device is configured to take a state that the first switch is on and the second switch is off, and
wherein the semiconductor device is configured that, after the first switch is turned on, the second switch is turned on so that a loop of the first inverter, the first switch, the second inverter, and the second switch is formed.

8. The semiconductor memory device according to claim 7 , wherein a transistor in the memory cell and a transistor in the first inverter are provided in different layers.

9. The semiconductor memory device according to claim 7 , wherein the switch comprises a plurality of transistors.

10. The semiconductor memory device according to claim 7 , wherein the switch comprises transistors with different conductivity types.

11. The semiconductor memory device according to claim 7 ,
wherein a channel area of an n-channel transistor included in the first inverter is from 80% to 125% of a channel area of a p-channel transistor included in the first inverter, and
wherein a value obtained by dividing a channel width by a channel length of the p-channel transistor is 2.5 times to 4 times as large as a value obtained by dividing a channel width by a channel length of the n-channel transistor.

12. The semiconductor memory device according to claim 7 , wherein a channel area of an n-channel transistor included in the first inverter is 10 F 2 or larger, where F is the feature size.

Assignees

• Semiconductor Energy Lab

Inventors

• Takemura Yasuhiko

Classifications

• G11C7/02 Primary

  with means for avoiding parasitic signals · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/08

  Control thereof · CPC title