Semiconductor device

Patent metadata

Field	Value
Publication number	US-9336850-B2
Application number	US-201414474454-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	May 19, 2011
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.

First claim

What is claimed is:

1. A semiconductor device comprising a memory cell, the memory cell including:
a memory;
a first transistor including an oxide semiconductor including indium in a channel formation region; and
a MOS capacitor,
wherein the first transistor is over the MOS capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to an output port of the memory, and
wherein the other of the source and the drain of the first transistor is electrically connected to the MOS capacitor.

2. The semiconductor device according to claim 1 , wherein the memory is a volatile memory.

3. The semiconductor device according to claim 1 ,
wherein the memory comprises a capacitor and a second transistor, and
wherein the second transistor includes a semiconductor including silicon.

4. The semiconductor device according to claim 1 , further comprising a pipeline circuit,
wherein an output of the pipeline circuit is connected to the memory cell.

5. A semiconductor device comprising a memory cell, the memory cell including:
a memory;
a first transistor including an oxide semiconductor including indium in a channel formation region; and
a first capacitor; and
a MOS capacitor,
wherein the first transistor is over the MOS capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to an output port of the memory, and
wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor and the MOS capacitor.

6. The semiconductor device according to claim 5 , wherein the memory is a volatile memory.

7. The semiconductor device according to claim 5 ,
wherein the memory comprises a second capacitor and a second transistor, and
wherein the second transistor includes a semiconductor including silicon.

8. The semiconductor device according to claim 5 , further comprising a pipeline circuit,
wherein an output of the pipeline circuit is connected to the memory cell.

9. A semiconductor device comprising a memory cell, the memory cell including:
a memory;
a first transistor including an oxide semiconductor including indium in a channel formation region; and
a first capacitor,
wherein the first transistor is over the first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to an output port of the memory, and
wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor.

10. The semiconductor device according to claim 9 , wherein the memory is a volatile memory.

11. The semiconductor device according to claim 9 ,
wherein the memory comprises a second capacitor and a second transistor, and
wherein the second transistor includes a semiconductor including silicon.

12. The semiconductor device according to claim 9 , further comprising a pipeline circuit,
wherein an output of the pipeline circuit is connected to the memory cell.

13. A semiconductor device comprising a memory cell, the memory cell including:
a memory;
a first transistor including an oxide semiconductor including indium in a channel formation region;
a second transistor including an oxide semiconductor including indium in a channel formation region; and
a first capacitor,
wherein each of the first transistor and the second transistor is over the first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to an output port of the memory,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, and
wherein the other of the source and the drain of the second transistor is electrically connected to the first capacitor.

14. The semiconductor device according to claim 13 , wherein the memory is a volatile memory.

15. The semiconductor device according to claim 13 ,
wherein the memory comprises a second capacitor and a third transistor, and
wherein the second transistor includes a semiconductor including silicon.

16. The semiconductor device according to claim 13 , further comprising a pipeline circuit,
wherein an output of the pipeline circuit is connected to the memory cell.

Assignees

• Semiconductor Energy Lab

Inventors

• Shionoiri Yutaka
• Kobayashi Hidetomo

Classifications

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C11/405

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title

• G11C11/24 Primary

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title