Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-2016006433-A1
Application number	US-201514755906-A
Country	US
Kind code	A1
Filing date	Jun 30, 2015
Priority date	Jul 4, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A semiconductor device with a novel structure is provided. In the semiconductor device executing a pipeline processing, a first arithmetic unit and a second arithmetic unit are provided for an execution stage, and transistors for performing power gating for the respective arithmetic units are provided. Only the arithmetic unit that performs an arithmetic operation is supplied with power supply voltage. Thus, fine-grained power gating can be performed, so that the power consumption of the semiconductor device can be reduced. In each of the transistors for performing power gating, a channel formation region includes an oxide semiconductor; thus, a reduction in leakage current between power supply lines can be achieved. Furthermore, these transistors and transistors in the arithmetic units can be provided in different layers, and thus an increase in area overhead due to the additionally provided transistors can be prevented.

First claim

What is claimed is:

1 . A semiconductor device executing a pipeline processing, comprising:
an instruction decode stage comprising a decoder; and an execution stage comprising a first arithmetic portion and a second arithmetic portion,
the first arithmetic portion comprising a first arithmetic unit and a first transistor that is connected to the first arithmetic unit and is provided between wirings through which power supply voltage is supplied to the first arithmetic unit, wherein supply of the power supply voltage to the first arithmetic unit depends on an on/off state of the first transistor,
the second arithmetic portion comprising a second arithmetic unit and a second transistor that is connected to the second arithmetic unit and is provided between the wirings through which the power supply voltage is supplied to the second arithmetic unit, wherein supply of the power supply voltage to the second arithmetic unit depends on an on/off state of the second transistor,
wherein the on/off state of each of the first transistor and the second transistor is controlled according to an instruction that is decoded in the decoder and supplied to a gate of each of the first transistor and the second transistor.

2 . The semiconductor device according to claim 1 , wherein a channel formation region of each of the first transistor and the second transistor comprises an oxide semiconductor.

3 . The semiconductor device according to claim 2 , wherein the oxide semiconductor comprises In, Ga, and Zn.

4 . The semiconductor device according to claim 1 , wherein the first transistor and the second transistor are respectively provided over the first arithmetic unit and the second arithmetic unit with an insulating layer provided therebetween.

5 . The semiconductor device according to claim 1 , wherein the first arithmetic unit is designed to execute an instruction for addition and subtraction, and the second arithmetic unit is designed to execute an instruction for multiplication.

6 . The semiconductor device according to claim 1 ,
wherein the first arithmetic unit comprises an inverter and a p-channel transistor, wherein the gate of the first transistor is electrically connected to a gate of the p-channel transistor, and wherein one of a source and a drain of the p-channel transistor is electrically connected to an output terminal of the inverter.

7 . An electronic device comprising:
the semiconductor device according to claim 1 ; and a display device or a speaker.

8 . A semiconductor device executing a pipeline processing, comprising:
an instruction decode stage comprising a decoder; and an execution stage comprising a first arithmetic portion and a second arithmetic portion,
the first arithmetic portion comprising a first arithmetic unit and a first transistor that is connected to the first arithmetic unit and is provided between wirings through which power supply voltage is supplied to the first arithmetic unit, wherein supply of the power supply voltage to the first arithmetic unit depends on an on/off state of the first transistor,
the second arithmetic portion comprising a second arithmetic unit and a second transistor that is connected to the second arithmetic unit and is provided between the wirings through which the power supply voltage is supplied to the second arithmetic unit, wherein supply of the power supply voltage to the second arithmetic unit depends on an on/off state of the second transistor,
wherein the on/off state of each of the first transistor and the second transistor is controlled according to an instruction that is decoded in the decoder and supplied to a gate of each of the first transistor and the second transistor, wherein the first arithmetic unit and the second arithmetic unit each comprises a third transistor, and wherein the first transistor and the second transistor are provided in a different layer from a layer in which the third transistor is provided.

9 . The semiconductor device according to claim 8 , wherein a channel formation region of each of the first transistor and the second transistor comprises an oxide semiconductor.

10 . The semiconductor device according to claim 9 , wherein the oxide semiconductor comprises In, Ga, and Zn.

11 . The semiconductor device according to claim 8 , wherein a channel formation region of the third transistor comprises silicon.

12 . The semiconductor device according to claim 8 , wherein a source electrode or a drain electrode of the third transistor has a region overlapping with a source electrode or a drain electrode of the first transistor or the second transistor.

13 . The semiconductor device according to claim 8 , wherein the first transistor and the second transistor are respectively provided over the first arithmetic unit and the second arithmetic unit with an insulating layer provided therebetween.

14 . The semiconductor device according to claim 8 , wherein the first arithmetic unit is designed to execute an instruction for addition and subtraction, and the second arithmetic unit is designed to execute an instruction for multiplication.

15 . The semiconductor device according to claim 8 ,
wherein the first arithmetic unit comprises an inverter and a p-channel transistor, wherein the gate of the first transistor is electrically connected to a gate of the p-channel transistor, and wherein one of a source and a drain of the p-channel transistor is electrically connected to an output terminal of the inverter.

16 . An electronic device comprising:
the semiconductor device according to claim 8 ; and a display device or a speaker.

Assignees

• Semiconductor Energy Lab

Inventors

• Ishizu Takahiko
• Uesugi Wataru

Classifications

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title