Method for driving arithmetic processing unit

Patent metadata

Field	Value
Publication number	US-9245593-B2
Application number	US-201414514638-A
Country	US
Kind code	B2
Filing date	Oct 15, 2014
Priority date	Oct 16, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

In a memory cell including an inverter, a capacitor is provided. When the memory cell is not accessed, data stored in the memory cell is copied to the capacitor and then power supply to the inverter is stopped. When the memory cell needs to be accessed, the data is returned from the capacitor to the inverter. In this manner, power consumption when the memory cell is not accessed is reduced. Furthermore, in a memory device including a plurality of such memory cells, backup of the first memory cell and backup of the second memory cell are performed at different timings. Recovery of the first memory cell and recovery of the second memory cell are also performed at different timings. Consequently, power required for backup or recovery can be distributed. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A method for driving an arithmetic processing unit, the arithmetic processing unit including a first memory cell and a second memory cell, the first memory cell and the second memory cell each including: a transistor; a capacitor; a first inverter an output of which is input to the capacitor through the transistor; and a second inverter an output of which is directly or indirectly input to the first inverter and an input of which is directly or indirectly output from the first inverter, the method comprising the steps of:
turning on the transistor of the first memory cell at a first time;
stopping power supply to at least one of the first inverter and the second inverter of the first memory cell at a second time;
turning on the transistor of the second memory cell at a third time; and
stopping power supply to at least one of the first inverter and the second inverter of the second memory cell at a fourth time,
wherein the first time is earlier than the third time, and
wherein the second time is earlier than the fourth time.

2. The method according to claim 1 , further comprising the steps of:
turning off the transistor of the first memory cell between the first time and the second time; and
turning off the transistor of the second memory cell between the third time and the fourth time.

3. The method according to claim 1 , wherein the second time is later than the third time and earlier than the fourth time.

4. The method according to claim 1 ,
wherein the transistor of the first memory cell and the transistor of the second memory cell include an oxide semiconductor, and
wherein a channel formation region is in the oxide semiconductor.

5. The method according to claim 1 ,
wherein the transistor of the first memory cell and the transistor of the second memory cell include a semiconductor film, and
wherein a channel formation region is in the semiconductor film.

6. The method according to claim 1 , further comprising the steps of:
turning on a transistor of a third memory cell at a fifth time; and
turning on a transistor of a fourth memory cell at a sixth time,
wherein power supply to at least one of a first inverter and a second inverter of the third memory cell is stopped at the second time,
wherein power supply to at least one of a first inverter and a second inverter of the fourth memory cell is stopped at the fourth time,
wherein the fifth time is earlier than the third time,
wherein the sixth time is earlier than the fourth time, and
wherein, in each of the third memory cell and the fourth memory cell, an output of the first inverter is input to a capacitor through the transistor, and an output of the second inverter is directly or indirectly input to the first inverter and an input of the second inverter is directly or indirectly input from the first inverter.

7. A method for driving an arithmetic processing unit, the arithmetic processing unit including a first memory cell and a second memory cell, the first memory cell and the second memory cell each including: a transistor; a capacitor; a first inverter an output of which is input to the capacitor through the transistor; and a second inverter an output of which is directly or indirectly input to the first inverter and an input of which is directly or indirectly output from the first inverter, the method comprising the steps of:
turning on the transistor of the first memory cell at a first time;
starting power supply to at least one of the first inverter and the second inverter of the first memory cell at a second time;
turning on the transistor of the second memory cell at a third time; and
starting power supply to at least one of the first inverter and the second inverter of the second memory cell at a fourth time,
wherein the first time is earlier than the third time, and
wherein the second time is earlier than the fourth time.

8. The method according to claim 7 , further comprising the steps of:
turning off the transistor of the first memory cell after the second time; and
turning off the transistor of the second memory cell after the fourth time.

9. The method according to claim 7 , wherein the second time is later than the third time and earlier than the fourth time.

10. The method according to claim 7 ,
wherein the transistor of the first memory cell and the transistor of the second memory cell include an oxide semiconductor, and
wherein a channel formation region is in the oxide semiconductor.

11. The method according to claim 7 ,
wherein the transistor of the first memory cell and the transistor of the second memory cell include a semiconductor film, and
wherein a channel formation region is in the semiconductor film.

12. The method according to claim 7 , further comprising the steps of:
turning on a transistor of a third memory cell at a fifth time; and
turning on a transistor of a fourth memory cell at a sixth time,
wherein power supply to at least one of a first inverter and a second inverter of the third memory cell is started at the second time,
wherein power supply to at least one of a first inverter and a second inverter of the fourth memory cell is started at the fourth time,
wherein the fifth time is earlier than the third time,
wherein the sixth time is earlier than the fourth time, and
wherein, in each of the third memory cell and the fourth memory cell, an output of the first inverter is input to a capacitor through the transistor, and an output of the second inverter is directly or indirectly input to the first inverter and an input of the second inverter is directly or indirectly input from the first inverter.

13. A method for driving an arithmetic processing unit, the arithmetic processing unit including a first memory cell and a second memory cell, the first memory cell and the second memory cell each including: a transistor; a capacitor; a first inverter an output of which is input to the capacitor through the transistor; and a second inverter an output of which is directly or indirectly input to the first inverter and an input of which is directly or indirectly output from the first inverter, the method comprising the steps of:
turning on the transistor of the first memory cell at a first time,
stopping power supply to at least one of the first inverter and the second inverter of the first memory cell at a second time;
turning on the transistor of the second memory cell at a third time;
stopping power supply to at least one of the first inverter and the second inverter of the second memory cell at a fourth time;
turning on the transistor of the first memory cell at a fifth time;
starting power supply to at least one of the first inverter and the second inverter of the first memory cell at a sixth time;
turning on the transistor of the second memory cell at a seventh time; and
starting power supply to at least one of the first inverter and the second inverter of the second memory cell at an eighth time,
wherein the first time is earlier than the third time,
wherein the second time is earlier than the fourth time,
wherein the fifth time is earlier than the seventh time, and
wherein the sixth time is earlier than the eighth time.

14. The method according to claim 13 , further comprising the steps of:
turning off the transistor of the first memory cell between the first time and the second time;
turning off the transistor of the second memory cell between the third time and the fourth time;
turning off the transistor of the first memory cell after the sixth time; and
turning off the transistor of the second memory cell after the eighth time.

Assignees

• Semiconductor Energy Lab

Inventors

• Ishizu Takahiko

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title