Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10032787-B2
Application number	US-201715652411-A
Country	US
Kind code	B2
Filing date	Jul 18, 2017
Priority date	Nov 26, 2013
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device comprising:
a plurality of stacked structures formed on a semiconductor layer of a first conductivity type, wherein each of the stacked structures includes a plurality of electrodes vertically stacked on each other and is extended in a first direction;
a plurality of vertical semiconductor patterns penetrating the plurality of stacked structures;
a plurality of common source regions of a second conductivity type disposed in the semiconductor layer, wherein at least one common source region of the plurality of common source regions is disposed between two adjacent stacked structures of the plurality of stacked structures, and the at least one common source region is extended in the first direction; and
a plurality of well pickup regions of the first conductivity type disposed in the semiconductor layer,
wherein at least one well pickup region of the plurality of well pickup regions is adjacent to stacked structure of the plurality of stacked structures, and
wherein the plurality of vertical semiconductor patterns are nearer to the plurality of common source regions than the plurality of immediately adjacent well pickup regions.

2. The three-dimensional semiconductor memory device of claim 1 , wherein vertical depths of the at least one common source region and at least one well pickup region are substantially equal to thickness of the semiconductor layer.

3. The three-dimensional semiconductor memory device of claim 1 , wherein at least one well pick up region of the plurality of well pickup regions is disposed between two adjacent common source regions of the plurality of common source regions.

4. The three-dimensional semiconductor memory device of claim 1 , wherein the plurality of well pick up regions includes at least one well pick up region disposed underneath of the at least one stacked structure.

5. The three-dimensional semiconductor memory device of claim 1 , further comprising:
a peripheral logic structure including a lower filling insulating layer and peripheral circuits,
wherein the lower filling insulating layer covers the peripheral circuits, and
wherein the semiconductor layer is disposed on a top surface of the lower filling insulating layer.

6. The three-dimensional semiconductor memory device of claim 5 ,
wherein at least one of the plurality of vertical semiconductor patterns includes a lower semiconductor pattern and an upper semiconductor pattern,
wherein the lower semiconductor pattern is disposed on a sidewall of a lowermost electrode in the plurality of electrodes, and
wherein the upper semiconductor pattern is disposed on an upper surface of the lower semiconductor pattern.

7. The three-dimensional semiconductor memory device of claim 6 ,
wherein the lower semiconductor pattern penetrates the semiconductor layer to be in contact with the lower filling insulating layer.

8. The three-dimensional semiconductor memory device of claim 5 , further comprising:
a connection contact plug penetrating the semiconductor layer to electrically connect the peripheral logic structure and the plurality of stacked structures to each other.

9. A three-dimensional semiconductor memory device comprising:
a plurality of stacked structures formed on a semiconductor layer of a first conductivity type, wherein each of the stacked structures includes a plurality of electrodes vertically stacked on each other and is extended in a first direction;
a plurality of vertical semiconductor patterns penetrating the plurality of stacked structures;
a plurality of common source regions of a second conductivity type disposed in the semiconductor layer, wherein at least one common source region of the plurality of common source regions is disposed between two adjacent stacked structures of the plurality of stacked structures, and the at least one common source region is extended in the first direction; and
a plurality of well pickup regions of the first conductivity type disposed in the semiconductor layer,
a peripheral logic structure including a lower filling insulating layer and peripheral circuits,
wherein the lower filling insulating layer covers the peripheral circuits,
wherein the semiconductor layer is disposed on a top surface of the lower filling insulating layer,
wherein at least one well pickup region of the plurality of well pickup regions is adjacent to stacked structure of the plurality of stacked structures.

10. The three-dimensional semiconductor memory device of claim 9 , wherein vertical depths of the at least one common source region and at least one well pickup region are substantially equal to thickness of the semiconductor layer.

11. The three-dimensional semiconductor memory device of claim 9 , wherein at least one well pick up region of the plurality of well pickup regions is disposed between two adjacent common source regions of the plurality of common source regions.

12. The three-dimensional semiconductor memory device of claim 9 , wherein the plurality of well pick up regions includes at least one well pick up region disposed underneath of the at least one stacked structure.

13. The three-dimensional semiconductor memory device of claim 9 ,
wherein at least one of the plurality of vertical semiconductor patterns includes a lower semiconductor pattern and an upper semiconductor pattern,
wherein the lower semiconductor pattern is disposed on a sidewall of a lowermost electrode in the plurality of electrodes, and
wherein the upper semiconductor pattern is disposed on an upper surface of the lower semiconductor pattern.

14. The three-dimensional semiconductor memory device of claim 13 ,
wherein the lower semiconductor pattern penetrates the semiconductor layer to be in contact with the lower filling insulating layer.

15. The three-dimensional semiconductor memory device of claim 9 , further comprising;
a connection contact plug penetrating the semiconductor layer to electrically connect the peripheral logic structure and the plurality of stacked structures to each other.

16. A three-dimensional semiconductor memory device comprising;
a plurality of stacked structures formed on a semiconductor layer, wherein each of the stacked structures includes a plurality of electrodes vertically stacked on each other and is extended in a first direction;
a plurality of vertical semiconductor patterns penetrating the plurality of stacked structures;
a plurality of common source regions disposed on the semiconductor layer, wherein at least one common source region of the plurality of common source regions is disposed underneath the plurality of stacked structures, and the at least one common source region is extended in the first direction; and
a plurality of well pickup regions disposed underneath the plurality of stacked structures,
a peripheral logic structure including a lower filling insulating layer and peripheral circuits,
wherein the peripheral logic structure is disposed underneath the plurality of stacked structures, and
wherein the lower filling insulating layer covers the peripheral circuits.

17. The three-dimensional semiconductor memory device of claim 16 , further comprising:
a connection contact plug penetrating the semiconductor layer to electrically connect the peripheral logic structure and the plurality of stacked structures to each other.

18. The three-dimensional semiconductor memory device of claim 16 , wherein the plurality of vertical semiconductor patterns are nearer to the plurality of common source regions than t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Yoocheol
• Kim Hongsoo
• Sim Jaesung

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11575

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11548

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic