Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9484355-B2
Application number	US-201514801470-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Jul 23, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a cell array region and a peripheral circuit region;
a stack structure disposed on the cell array region, the stack structure including a plurality of electrodes and a plurality of insulating layers alternately stacked;
a plurality of first peripheral gate structures disposed on a first region of the peripheral circuit region and extended in a first direction, wherein the plurality of first peripheral gate structures is spaced apart from each other at a first distance along a second direction crossing the first direction;
a plurality of first residual spacers disposed in the first region, wherein at least two first residual spacers are interposed between two adjacent first peripheral gate structures;
a plurality of second peripheral gate structures disposed on a second region of the peripheral circuit region, wherein the plurality of second peripheral gate structures is spaced apart from each other at a second distance along the second direction;
a plurality of second residual spacers disposed in the second region, wherein one second residual spacer is interposed between two adjacent second peripheral gate structures;
a first peripheral contact plug connected to the substrate and interposed between at least two first residual spacers; and
a second peripheral contact plug connected to the substrate and penetrating one second residual spacer interposed between two adjacent second peripheral gate structures.

2. The semiconductor device of claim 1 , wherein top ends of the plurality of first residual spacers are disposed at substantially the same height as or a lower height than top surfaces of the plurality of first peripheral gate structures.

3. The semiconductor device of claim 1 , wherein end portions of the one second residual spacer face each other across the substrate between the two adjacent second peripheral gate structures.

4. The semiconductor device of claim 1 , further comprising:
a peripheral protection layer covering the plurality of first and second peripheral gate structures,
wherein the peripheral protection layer is interposed between the plurality of first and second peripheral gate structures and the plurality of first and second residual spacers.

5. The semiconductor device of claim 1 , wherein each of the plurality of first and second residual spacers comprises a sacrificial pattern and an insulating pattern that are stacked, and wherein the insulating pattern includes substantially the same material as the plurality of insulating layers of the stack structure.

6. A semiconductor device comprising:
a substrate including a cell array region and a peripheral circuit region;
a stack structure disposed on the cell array region, the stack structure including a plurality of electrodes and a plurality of insulating layers alternately stacked;
at least one peripheral gate structure disposed on the peripheral circuit region; and
at least one residual spacer on the substrate at one sidewall of the peripheral gate structure,
wherein the at least one residual spacer comprises a sacrificial pattern and an insulating pattern on the sacrificial pattern, and
wherein the insulating pattern includes substantially the same material as the plurality of insulating layers of the stack structure.

7. The semiconductor device of claim 6 ,
wherein the sacrificial pattern includes a material having etch selectivity with respect to the insulating pattern.

8. The semiconductor device of claim 6 ,
wherein the at least one residual spacer includes a sidewall portion covering the one sidewall of the peripheral gate structure and a bottom portion extending from the sidewall portion to cover a portion of the substrate.

9. The semiconductor device of claim 6 ,
wherein a top end of the at least one residual spacer is disposed at substantially the same height as or a lower height than a top surface of the at least one peripheral gate structure.

10. The semiconductor device of claim 6 , further comprising:
an additional peripheral gate structure disposed on the peripheral circuit region to be spaced apart from the at least one peripheral gate structure; and
an additional residual spacer disposed between the additional peripheral gate structure and the at least one peripheral gate structure,
wherein the additional residual spacer covers another sidewall of the peripheral gate structure and one sidewall of the additional peripheral gate structure.

11. The semiconductor device of claim 10 ,
wherein the additional residual spacer comprises sacrificial layer includes a material having etch selectivity with respect to the insulating layers.

12. The semiconductor device of claim 6 , further comprising:
a plurality of source/drain regions provided in the substrate and disposed in both sides of the at least one peripheral gate structure; and
a plurality of peripheral contact plugs connected to the plurality of source/drain regions,
wherein the at least one residual spacer and one of the plurality of source/drain regions overlap each other.

13. The semiconductor device of claim 12 ,
wherein at least one of the peripheral contact plugs penetrates the at least one residual spacer.

14. The semiconductor device of claim 6 , further comprising:
a peripheral protection layer covering the at least one peripheral gate structure,
wherein the peripheral protection layer is interposed between the at least one peripheral gate structure and the at least one residual spacer.

15. The semiconductor device of claim 14 ,
wherein the at least one peripheral gate structure comprises:
a peripheral gate pattern disposed on the substrate; and
a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern, and
wherein the peripheral protection layer includes a material having etch selectivity with respect to the peripheral gate spacer.

16. The semiconductor device of claim 6 , further comprising:
a plurality of vertical structures penetrating the stack structure to be connected to the substrate; and
a data storage layer disposed between the plurality of vertical structures and the plurality of electrodes of the stack structure,
wherein the plurality of vertical structures includes a semiconductor pattern.

17. A semiconductor device comprising:
a substrate including a cell array region and a peripheral circuit region;
a stack structure disposed on the cell array region, the stack structure including a plurality of electrodes and a plurality of insulating layers alternately stacked;
at least one peripheral gate structure disposed on the peripheral circuit region;
at least one residual spacer covering one sidewall of the at least one peripheral gate structure; and
a peripheral contact plug connected to the substrate and penetrating the at least one residual spacer,
wherein the at least one residual spacer comprises a sacrificial pattern and an insulating pattern that are stacked, and
wherein the insulating pattern includes substantially the same material as the plurality of insulating layers of the stack structure.

18. The semiconductor device of claim 17 ,
wherein the sacrificial pattern includes a material having etch selectivity with respect to the insulating pattern.

19. The semiconductor device of claim 17 , further comprising:
a peripheral protection layer covering the at least one peripheral gate structure,
wherein the peripheral protection layer is interposed between the at least one peripheral gate structure and t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Won-Seok
• Kang Changseok
• Paek Seungwoo
• Yang Inseok
• Joo Kyungjoong

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/511

  for IGFETs · CPC title

• H10D64/27

  Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates · CPC title

• H10D84/80 Primary

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H01L27/11573

  Electricity · mapped topic