Vertical gate-all-around tfet
US-2016293739-A1 · Oct 6, 2016 · US
Semiconductor device
US2016155751A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016155751-A1 |
| Application number | US-201615018477-A |
| Country | US |
| Kind code | A1 |
| Filing date | Feb 8, 2016 |
| Priority date | Nov 8, 2013 |
| Publication date | Jun 2, 2016 |
| Grant date | — |
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Abstract
Official abstract text for this publication.
A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.
First claim
Opening claim text (preview).
1 .- 20 . (canceled) 21 . A semiconductor device, comprising: a substrate including a memory cell array region; a memory cell array formed on the memory cell array region, the memory cell array including: a channel layer extending in a vertical direction on the substrate, and at least one ground selection line, at least one word line, and at least one string selection line spaced apart in the vertical direction along a sidewall of the channel layer; and at least o…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/0411Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2016155751A1 cover?
- A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through t…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0411. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jun 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).