Semiconductor device including cell region stacked on peripheral region and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2016307632-A1
Application number	US-201615049526-A
Country	US
Kind code	A1
Filing date	Feb 22, 2016
Priority date	Apr 16, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor device may include a peripheral region including a lower substrate and a peripheral circuit provided thereon and a cell region including an upper substrate and a cell array provided thereon. The cell region may be stacked on the peripheral region. When an operation signal is applied to the cell region from the peripheral region, at least a portion of the peripheral and cell regions may be used as a ground pattern applied with a ground signal, thereby being in an electrical ground state.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a cell-on-peripheral structure including a peripheral region and a cell region stacked thereon, wherein the peripheral region comprises a lower substrate, a peripheral circuit provided on the lower substrate, and a peripheral metal line electrically connected to the peripheral circuit, wherein the cell region comprises an upper substrate and a cell region overlapping the peripheral circuit, wherein the upper substrate includes a base substrate encompassing junction regions electrically connected to circuits in the cell region; and a grounding structure disposed between the base substrate and the peripheral metal line, the grounding structure providing an electrical ground during a memory cell erase operation.

2 . The device of claim 1 , wherein during the memory cell erase operation, a higher voltage is applied to the upper substrate than a voltage applied to the peripheral circuit.

3 . The device of claim 1 , wherein the grounding structure is a well structure encompassing the base substrate.

4 . The device of claim 3 , wherein the well structure includes a first well encompassing the base substrate and a second well encompassing the first well.

5 . The device of claim 3 , wherein the base substrate is a polysilicon layer doped with a first connectivity type, and the well structure includes at least one polysilicon layer doped with a second connectivity type.

6 . The device of claim 3 , wherein the base substrate is a polysilicon layer doped with a first connectivity type, and the first well is a polysilicon layer doped with a second connectivity type, and the second well is a polysilicon layer doped with the first connectivity type.

7 . The device of claim 1 , wherein the grounding structure is connected to ground via a plug.

8 . The device of claim 1 , wherein the grounding structure is a metal plate.

9 . The device of claim 8 , wherein the metal plate overlaps the entire cell region.

10 . The device of claim 8 , wherein the metal plate partially overlaps the cell region.

11 . The device of claim 8 , wherein the metal plate partially overlaps the cell region and overlaps the entire peripheral circuit.

12 . The device of claim 1 , wherein the cell region includes a 3D memory cell.

13 . The device of claim 3 , wherein the junction regions in the base substrate and junctions regions in the well structure are connected to metal lines via plugs.

14 . The device of claim 13 , wherein a higher voltage is applied to at least one junction region in the base substrate, and a ground voltage is applied to a junction region in the well.

15 . The device of claim 13 , further including a gate stack disposed on the base substrate, wherein the junction regions in the base substrate are disposed spaced apart and outside of opposing sides of the gate stack when viewed from above the gate stack toward the base substrate.

16 . The device of claim 15 , wherein the junction regions in the base substrate are connected to a metal line via respective plugs extending vertically from the junction regions.

17 . The device of claim 8 , wherein the metal plate is connected to a metal line in the cell region.

18 . The device of claim 8 , wherein the metal plate is connected to a metal line in the peripheral region.

19 . The device of claim 1 , wherein the cell region includes a vertical-type NAND memory device.

20 . The device of claim 1 , wherein a ground signal is selectively applied to the grounding structure to provide the electrical ground.

21 . A semiconductor device, comprising:
a cell-on-peripheral structure including a peripheral region and a cell region stacked thereon, wherein the peripheral region comprises a lower substrate, a peripheral circuit provided on the lower substrate, and a peripheral metal line electrically connected to the peripheral circuit, wherein the cell region comprises an upper substrate and a cell region overlapping the peripheral circuit, wherein the upper substrate includes a base substrate encompassing junction regions electrically connected to circuits in the cell region; and a grounding structure disposed between the base substrate and the peripheral metal line, the grounding structure provides an electrical ground during a memory operation.

22 . The device of claim 21 , wherein the memory operation is a cell erase operation, and a higher voltage is applied to the upper substrate than a voltage applied to the peripheral circuit.

23 . The device of claim 21 , wherein the grounding structure is a well structure encompassing the base substrate.

24 . The device of claim 23 , wherein the well structure includes a first well encompassing the base substrate and a second well encompassing the first well.

25 . The device of claim 23 , wherein the base substrate is a polysilicon layer doped with a first connectivity type, and the well structure includes at least one polysilicon layer doped with a second connectivity type.

26 . The device of claim 23 , wherein the base substrate is a polysilicon layer doped with a first connectivity type, and the first well is a polysilicon layer doped with a second connectivity type, and the second well is a polysilicon layer doped with the first connectivity type.

27 . The device of claim 21 , wherein the grounding structure is connected to ground via a plug.

28 . The device of claim 21 , wherein the grounding structure is a metal plate.

29 . The device of claim 28 , wherein the metal plate overlaps the entire cell region.

30 . The device of claim 28 , wherein the metal plate partially overlaps the cell region.

31 . The device of claim 28 , wherein the metal plate partially overlaps the cell region and overlaps the entire peripheral circuit.

32 . The device of claim 21 , wherein the cell region includes a 3D memory cell.

33 . The device of claim 21 , wherein the memory operation requires a higher voltage applied to the upper substrate than a voltage applied to the peripheral circuit.

34 . The device of claim 21 , wherein the electrical ground is selectively provided during a memory operation by application of a grounding signal to the grounding structure during the memory operation.

35 . A method of operating a semiconductor device having a cell-on-peripheral structure including a peripheral region and a cell region stacked thereon, wherein the peripheral region comprises a lower substrate, a peripheral circuit provided on the lower substrate, and a peripheral metal line electrically connected to the peripheral circuit,
wherein the cell region comprises an upper substrate and a cell region overlapping the peripheral circuit, wherein the upper substrate includes a base substrate encompassing junction regions electrically connected to circuits in the cell region, comprising: applying a ground to a grounding structure disposed between the base substrate and the peripheral metal line, and applying a first voltage to the base substrate and a second voltage to the peripheral circuit during a memory operation, wherein the first voltage is higher relative to the second voltage.

36 . The method of claim 35 , wherein the ground is applied to the ba

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Eun
• Kim Sunghoon

Classifications

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H01L23/53271

  Electricity · mapped topic