Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2016365356-A1
Application number	US-201615248564-A
Country	US
Kind code	A1
Filing date	Aug 26, 2016
Priority date	Jul 23, 2014
Publication date	Dec 15, 2016
Grant date	—

Abstract

A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
providing a substrate including a cell array region and a peripheral circuit region; forming at least one peripheral gate structure disposed on the peripheral circuit region, forming a thin layer structure by alternately and repeatedly stacking a plurality of sacrificial layers and a plurality of insulating layers on an entire top surface of the peripheral circuit region having the peripheral gate structure; and repeating a process of patterning the thin layer structure to sequentially expose top surfaces of the insulating layers between the cell array region and the peripheral circuit region to form a stack structure on the cell array region and at least one residual space on one sidewall of the peripheral gate structure.

2 . The method of claim 1 ,
wherein the at least one residual spacer comprises a sacrificial pattern and an insulating pattern on the sacrificial pattern, and wherein the insulating pattern includes substantially the same material as the plurality of insulating layers of the stack structure.

3 . The method of claim 2 ,
wherein the sacrificial pattern includes a material having etch selectivity with respect to the insulating pattern, and wherein the sacrificial pattern includes substantially the same material as the plurality of sacrificial layers of the stack structure.

4 . The method of claim 1 , further comprising:
forming a peripheral protection layer covering the peripheral gate structure before the forming of the thin layer structure, wherein the peripheral protection layer exposes the cell array region.

5 . The method of claim 4 , wherein the at least one peripheral gate structure comprises:
a peripheral gate pattern disposed on the substrate; and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern, wherein the peripheral protection layer includes a material having etch selectivity with respect to the peripheral gate spacer.

6 . The method of claim 1 , further comprising:
forming source/drain regions in the substrate at both sides of the at least one peripheral gate structure before the forming of the thin layer structure, wherein the at least one residual spacer overlaps with one of the source/drain regions.

7 . The method of claim 6 , further comprising:
forming a plurality of peripheral contact plugs connected to the source/drain regions, wherein at least one of the peripheral contact plugs penetrates the at least one residual spacer.

8 . The method of claim 1 , further comprising:
a plurality of vertical structures penetrating the stack structure on the cell array region; and a data storage layer disposed between the plurality of vertical structures and the stack structure.

9 . A method of fabricating a semiconductor device, the method comprising:
providing a substrate including a cell array region and a peripheral circuit region; forming at least one peripheral gate structure disposed on the peripheral circuit region, forming a thin layer structure by alternately and repeatedly stacking a plurality of sacrificial layers and a plurality of insulating layers on the cell array region and the peripheral circuit region; and repeating a process of patterning the thin layer structure to form a stack structure having a stair-step structure between the cell array region and the peripheral circuit region and at least one residual spacer on one sidewall of the peripheral gate structure, wherein the at least one residual spacer comprises a portion of at least one of sacrificial layers and a portion of at least one of insulating layers.

10 . The method of claim 9 , further comprising:
forming a peripheral protection layer covering the at least one peripheral gate structure before the forming of the thin layer structure, wherein the peripheral protection layer exposes the cell array region.

11 . The method of claim 9 , further comprising:
forming source/drain regions in the substrate at both sides of the at least one peripheral gate structure before the forming of the thin layer structure, wherein the at least one residual spacer overlaps with one of the source/drain regions.

12 . The method of claim 10 , further comprising:
forming a plurality of peripheral contact plugs connected to the source/drain regions, wherein at least one of the peripheral contact plugs penetrates the at least one residual spacer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Won-Seok
• Kang Changseok
• Paek Seungwoo
• Yang Inseok
• Joo Kyungjoong

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/511

  for IGFETs · CPC title

• H10D64/27

  Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates · CPC title

• H10D84/80 Primary

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H01L27/11575

  Electricity · mapped topic