Substrate connection of three dimensional NAND for improving erase performance

Patent metadata

Field	Value
Publication number	US-9117526-B2
Application number	US-201414165180-A
Country	US
Kind code	B2
Filing date	Jan 27, 2014
Priority date	Jul 8, 2013
Publication date	Aug 25, 2015
Grant date	Aug 25, 2015

Abstract

A memory includes a doped substrate well, a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well. A series arrangement including a plurality of memory cells is coupled on a first end by a first switch to a bit line and coupled on a second end by a second switch to a source line contact pad. The source line contact pad is connected to the substrate connector and to at least one of the interlayer connectors in the set of interlayer connectors. A supply line is connected to the set of interlayer connectors. A plurality of word lines is coupled to the plurality of memory cells. Circuitry is coupled to the supply line and to the doped substrate well and configured to bias the supply line and the doped substrate well with different bias conditions.

First claim

What is claimed is:

1. A memory comprising:
a doped substrate well;
a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well;
a series arrangement including a plurality of memory cells, the series arrangement coupled on a first end by a first switch to a bit line and coupled on a second end by a second switch to a source line contact pad, wherein the source line contact pad is connected to the substrate connector and to at least one of the interlayer connectors in the set of interlayer connectors;
a supply line connected to the set of interlayer connectors;
a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and
circuitry coupled to the supply line and to the doped substrate well and configured to bias the supply line and the doped substrate well with different bias conditions.

2. The memory of claim 1 , comprising a pickup contact to the doped substrate well, to which the circuitry is connected for biasing the doped substrate well.

3. The memory of claim 1 , wherein the circuitry is configured to apply an erase bias arrangement that induces hole tunneling, the erase bias arrangement including a source side bias on the doped substrate well, while the supply line remains floating, and erase voltages on the plurality of word lines that induce hole tunneling.

4. The memory of claim 3 , wherein the erase voltages on the plurality of word lines is non-negative.

5. The memory of claim 1 , wherein the circuitry is configured to apply a program bias arrangement that induces electron tunneling, the program bias arrangement including a source side bias on the supply line and the doped substrate well, and program voltages on the plurality of word lines that induce electron tunneling.

6. The memory of claim 1 , wherein the doped substrate well includes p-type doping, and the set of interlayer connectors includes n-type doping.

7. The memory of claim 1 , wherein the series arrangement is a NAND string, the memory including at least one additional NAND string coupled to the substrate connector.

8. The memory of claim 1 , wherein the plurality of memory cells comprises thin film transistor cells arranged on a single semiconductor strip which overlies the doped substrate well.

9. The memory of claim 1 , wherein the plurality of memory cells comprises thin film, vertical gate cells.

10. A memory comprising:
a 3D array including a plurality of levels, each level including a pad and a plurality of strips of semiconductor material extending from the pad;
a doped substrate well;
a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well, contacting one or more strips on an end distal of the pads in the plurality of levels;
a supply line connected to the set of interlayer connectors;
a plurality of word lines coupled to the plurality of strips in the plurality of levels;
charge-trapping, data storage elements between the word lines in the plurality of word lines and the strips of semiconductor material, whereby memory cells are disposed at cross-points of the strips and the word lines; and
circuitry coupled to the supply line and to the doped substrate well and configured to bias the supply line and the doped substrate well with different bias conditions.

11. The memory of claim 10 , comprising a pickup contact to the doped substrate well, to which the circuitry is connected for biasing the doped substrate well.

12. The memory of claim 10 , wherein the circuitry is configured to apply an erase bias arrangement that induces hole tunneling, the erase bias arrangement including a source side bias on the doped substrate well, while the supply line remains floating, and erase voltages on the plurality of word lines that induce hole tunneling.

13. The memory of claim 12 , wherein the erase voltages on the plurality of word lines is non-negative.

14. The memory of claim 10 , wherein the circuitry is configured to apply a program bias arrangement that induces electron tunneling, the program bias arrangement including a source side bias on the supply line and the doped substrate well, and program voltages on the plurality of word lines that induce electron tunneling.

15. The memory of claim 10 , including a plurality of first select lines coupled to respective stacks of strips in the plurality of strips proximal to the pads, and a second select line overlying the plurality of strips between the substrate connector and the plurality of word lines.

16. The memory of claim 10 , wherein the doped substrate well includes p-type doping, and the set of interlayer connectors includes n-type doping.

17. The memory of claim 10 , wherein the plurality of levels overlies the doped substrate well.

18. The memory of claim 10 , wherein the plurality of memory cells comprises thin film, vertical gate cells.

Assignees

• Macronix Int Co Ltd

Inventors

• Lai Erh-Kun

Classifications

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title