Line buffer unit for image processor
US-11190718-B2 · Nov 30, 2021 · US
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Zhu Qiuling patents
Zhu Qiuling is listed as an inventor on 62 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Zhu Qiuling |
| Total patents | 62 |
| First publication | Jul 16, 2015 |
| Latest publication | Nov 30, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Two dimensional shift array for image processor
US-11153464-B2 · Oct 19, 2021 · US
Energy efficient processor core architecture for image processor
US-11138013-B2 · Oct 5, 2021 · US
Sheet generator for image processor
US-11140293-B2 · Oct 5, 2021 · US
Energy Efficient Processor Core Architecture for Image Processor
US-2021004232-A1 · Jan 7, 2021 · US
Image processor with high throughput internal communication protocol
US-10872393-B2 · Dec 22, 2020 · US
Virtual linebuffers for image signal processors
US-10791284-B2 · Sep 29, 2020 · US
Line Buffer Unit for Image Processor
US-2020275040-A1 · Aug 27, 2020 · US
Energy efficient processor core architecture for image processor
US-10754654-B2 · Aug 25, 2020 · US
Architecture for high performance, power efficient, programmable image processing
US-10719905-B2 · Jul 21, 2020 · US
Recent patents
Latest publications not already listed above.
Compiler managed memory for image processor
US-10685422-B2 · Jun 16, 2020 · US
Determination of per line buffer unit memory allocation
US-10685423-B2 · Jun 16, 2020 · US
Sheet Generator For Image Processor
US-2020186667-A1 · Jun 11, 2020 · US
Line buffer unit for image processor
US-10638073-B2 · Apr 28, 2020 · US
Virtual linebuffers for image signal processors
US-2020120287-A1 · Apr 16, 2020 · US
Determination of per line buffer unit memory allocation
US-2020098083-A1 · Mar 26, 2020 · US
Sheet generator for image processor
US-10560598-B2 · Feb 11, 2020 · US
Virtual linebuffers for image signal processors
US-10516833-B2 · Dec 24, 2019 · US
Architecture for high performance, power efficient, programmable image processing
US-2019378239-A1 · Dec 12, 2019 · US
Two Dimensional Shift Array for Image Processor
US-2019364174-A1 · Nov 28, 2019 · US
Line Buffer Unit for Image Processor
US-2019327433-A1 · Oct 24, 2019 · US
Determination of per line buffer unit memory allocation
US-10430919-B2 · Oct 1, 2019 · US
Architecture for high performance, power efficient, programmable image processing
US-10417732-B2 · Sep 17, 2019 · US
Two dimensional shift array for image processor
US-10397450-B2 · Aug 27, 2019 · US
Virtual linebuffers for image signal processors
US-2019238758-A1 · Aug 1, 2019 · US
Energy Efficient Processor Core Architecture for Image Processor
US-2019220282-A1 · Jul 18, 2019 · US
Sheet Generator For Image Processor
US-2019208075-A1 · Jul 4, 2019 · US
Compiler managed memory for image processor
US-2019188824-A1 · Jun 20, 2019 · US
Line buffer unit for image processor
US-10321077-B2 · Jun 11, 2019 · US
Compiler managed memory for image processor
US-10304156-B2 · May 28, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Google Llc | 38 |
| Google Inc | 22 |
| Univ Carnegie Mellon | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 46 |
| G06T1/60 | 46 |
| H04N5/14 | 20 |
| G06F9/30134 | 20 |
| G06F9/30043 | 20 |