Energy efficient processor core architecture for image processor

Patent metadata

Field	Value
Publication number	US-10754654-B2
Application number	US-201916368288-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Apr 23, 2015
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

First claim

The invention claimed is:

1. A computing device comprising:
an array of execution lanes;
a scalar lane;
a two-dimensional shift-register array; and
a sheet generator configured to load sheets of data into the two-dimensional shift register array, wherein the computing device is configured to perform operations comprising:
receiving, by the scalar lane, an instruction specifying an operation to be performed using an operand having a first bit width, wherein the first bit width is wider than a second bit width of shift registers in the shift-register array;
issuing one or more instructions to the sheet generator that cause the sheet generator to load a high sheet and a low sheet into the shift-register array of the computing device; and
providing, by the scalar lane to each of the execution lanes in the execution lane array, one or more instructions to perform the operation using the operand having the first bit width using data from the high sheet and the low sheet loaded into the shift-register array.

2. The computing device of claim 1 , wherein the execution lanes are configured to use data from the high sheet and the low sheet loaded into the shift-register array by performing operations comprising:
performing a first read from the high sheet stored in the shift-register array to obtain a first portion of the operand; and
performing a second read from the low sheet stored in the shift-register array to obtain a second portion of the operand.

3. The computing device of claim 2 , wherein the execution lanes are configured to store respective portions of the result of executing the one or more instructions into the high sheet and the low sheet of the shift-register array by performing operations comprising:
performing a first write of a first portion of the result to the high sheet stored in the shift-register array; and
performing a second write of a second portion of the result to the low sheet stored in the shift-register array.

4. The computing device of claim 3 , wherein the scalar lane is configured to receive a shift instruction that specifies shifting data in the high sheet and the low sheet in the shift-register array and wherein the scalar lane is configured to issue multiple shift instructions to each execution lane to separately shift the high sheet and the low sheet in a same direction.

5. The computing device of claim 1 , wherein the first bit width of the operand is twice the second bit width of the shift registers.

6. The computing device of claim 1 , wherein the first bit width of the operand is four times the second bit width of the shift registers.

7. The computing device of claim 6 , wherein the execution lanes are configured to use data from two additional sheets of data loaded into the shift-register array by performing operations comprising:
performing a first read from a first additional sheet stored in the shift-register array to obtain a first portion of the operand; and
performing a second read from a second additional sheet stored in the shift-register array to obtain a second portion of the operand.

8. A method performed by computing device having an array of execution lanes, a scalar lane, a two-dimensional shift-register array, and a sheet generator configured to load sheets of data into the two-dimensional shift-register array, the method comprising:
receiving, by the scalar lane, an instruction specifying an operation to be performed using an operand having a first bit width, wherein the first bit width is wider than a second bit width of shift registers in the shift-register array;
issuing one or more instructions to the sheet generator that cause the sheet generator to load a high sheet and a low sheet into the shift-register array of the computing device; and
providing, by the scalar lane to each of the execution lanes in the execution lane array, one or more instructions to perform the operation using the operand having the first bit width using data from the high sheet and the low sheet loaded into the shift-register array.

9. The method of claim 8 , further comprising using, by the execution lanes, data from the high sheet and the low sheet loaded into the shift-register array comprising:
performing a first read from the high sheet stored in the shift-register array to obtain a first portion of the operand; and
performing a second read from the low sheet stored in the shift-register array to obtain a second portion of the operand.

10. The method of claim 9 , further comprising storing, by the execution lanes, respective portions of the result of executing the one or more instructions into the high sheet and the low sheet of the shift-register array comprising:
performing a first write of a first portion of the result to the high sheet stored in the shift-register array; and
performing a second write of a second portion of the result to the low sheet stored in the shift-register array.

11. The method of claim 10 , further comprising:
receiving, by the scalar lane, a shift instruction that specifies shifting data in the high sheet and the low sheet in the shift-register array; and
issuing, by the scalar lane, multiple shift instructions to each execution lane to separately shift the high sheet and the low sheet in a same direction.

12. The method of claim 8 , wherein the first bit width of the operand is twice the second bit width of the shift registers.

13. The method of claim 8 , wherein the first bit width of the operand is four times the second bit width of the shift registers.

14. The method of claim 13 , further comprising using, by the execution lanes, data from two additional sheets of data loaded into the shift-register array comprising:
performing a first read from a first additional sheet stored in the shift-register array to obtain a first portion of the operand; and
performing a second read from a second additional sheet stored in the shift-register array to obtain a second portion of the operand.

15. One or more non-transitory computer storage media encoded with instructions to be executed by a computing device comprising an array of execution lanes, a scalar lane, a two-dimensional shift-register array, and a sheet generator configured to load sheets of data into the two-dimensional shift register array,
wherein the instructions comprise an instruction specifying an operation to be performed using an operand having a first bit width, wherein the first bit width is wider than a second bit width of shift registers in the shift-register array, and wherein executing the instruction causes the computing device to perform operations comprising:
issuing one or more instructions to the sheet generator that cause the sheet generator to load a high sheet and a low sheet into the shift-register array of the computing device; and
providing, by the scalar lane to each of the execution lanes in the execution lane array, one or more instructions to perform the operation using the operand having the first bit width using data from the high sheet and the low sheet loaded into the shift-register array.

16. The one or more non-transitory computer storage media of claim 15 , wherein the operations further comprise using, by the execution lanes, data from the high sheet and the low sheet loaded into the shift-register array comprising:
performing a first read from the high sheet stored in the shift-register array to obtain a first portion of the operand; and
performing a second read from the low sheet stored in the shift-register array to obtain a second portion of the operand.

17. The one or more non-transitor

Assignees

• Google Llc

Inventors

• Meixner Albert
• Redgrave Jason Rupert
• Shacham Ofer
• Finchelstein Daniel Frederic
• Zhu Qiuling

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• H04N3/14

  by means of electrically scanned solid-state devices (for picture generation H04N25/00) · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title