Line buffer unit for image processor

Patent metadata

Field	Value
Publication number	US-11190718-B2
Application number	US-202016859308-A
Country	US
Kind code	B2
Filing date	Apr 27, 2020
Priority date	Apr 23, 2015
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

First claim

The invention claimed is:

1. A device configured to manage a pool of line group buffers for multiple different stencil processors, the device comprising:
a plurality of stencil processors;
a memory device configured to store line group data for the pool of line group buffers; and
a plurality of line buffer interface units, each line buffer interface unit being configurable to manage read and write requests for a respective line group buffer of the pool of line group buffers stored by the memory device, each line group buffer being a respective partition of storage within the memory device,
wherein the device is configured to reassign line buffer interface units to manage respective line group buffers for different stencil processors of the device after managing one or more of a plurality of line groups,
wherein reassigning a line buffer interface unit comprises:
selecting the line buffer interface unit from the plurality of line buffer interface units,
configuring the selected line buffer interface unit with configuration information including position information or a linear memory address of one of the plurality of line groups,
storing one of the plurality of line groups in the memory device according to the configuration information, and
providing the stored line group from the memory device according to the configuration information.

2. The device of claim 1 , wherein the device is configured to manage the pool of line group buffers for multiple different stencil processors executing different stages of a same image processing pipeline.

3. The device of claim 1 , wherein the device is configured to manage the pool of line group buffers for multiple different stencil processors executing different image processing pipelines.

4. The device of claim 1 , wherein the line buffer interface unit of the plurality of line buffer interface units is configured to receive a write request from one or more producer processors of the multiple stencil processors, to identify, within a line group buffer assigned to the line buffer interface unit and stored by the memory device, a write location corresponding to the write request, and to store data at the write location within the line group buffer assigned to the line buffer interface unit.

5. The device of claim 4 , wherein the line buffer interface unit of the plurality of line buffer interface units is configured to receive a read request from one or more consumer processors of the multiple stencil processors, to identify, within the line group buffer assigned to the line buffer interface unit and stored by the memory device, a read location corresponding to the read request, and to provide data stored at the read location within the line group buffer assigned to the line buffer interface unit.

6. The device of claim 5 , wherein, based on determining that a last producer processor has written to the plurality of the line groups and a last consumer processor has been provided with data stored at corresponding line group, the device is configured to return the line buffer interface unit to a line buffer interface units pool and is configured to proceed to a next line group of the plurality of line groups.

7. The device of claim 4 , wherein the configuration information comprises configuration parameters that specify respective sizes of line group buffers managed by the line buffer interface units and that are based on output sizes of respective kernel programs that provide write requests to the line buffer interface units.

8. The device of claim 7 , wherein the configuration parameters are stored in a respective programmable configuration space of each respective line buffer interface unit.

9. The device of claim 1 , wherein the device is configured to reassign the line buffer interface unit to manage a different line group buffer stored by the memory device.

10. A method for managing a pool of line group buffers for multiple different stencil processors, the method being performed by a device comprising a plurality of stencil processors, a memory device configured to store line group data for the pool of line group buffers, and a plurality of line buffer interface units, the method comprising:
managing, by each line buffer interface unit, read and write requests for a respective line group buffer of the pool of line group buffers stored by the memory device, each line group buffer being a respective partition of storage within the memory device; and
reassigning line buffer interface units to manage respective line group buffers for different stencil processors of the device after managing one or more of a plurality of line groups,
wherein reassigning a line buffer interface unit comprises:
selecting the line buffer interface unit from the plurality of line buffer interface units,
configuring the selected line buffer interface unit with configuration information including position information or a linear memory address of one of the plurality of line groups,
storing one of the plurality of line groups in the memory device according to the configuration information, and
providing the stored line group from the memory device according to the configuration information.

11. The method of claim 10 , further comprising managing the pool of line group buffers for multiple different stencil processors executing different stages of a same image processing pipeline.

12. The method of claim 10 , further comprising managing the pool of line group buffers for multiple different stencil processors executing different image processing pipelines.

13. The method of claim 10 , wherein configuration parameters that specify the respective sizes of line group buffers managed by the line buffer interface units are based on output sizes of respective kernel programs that provide write requests to the line buffer interface units.

14. The method of claim 13 , further comprising storing the configuration parameters that specify the respective sizes of line group buffers managed by the line buffer interface units in a respective programmable configuration space of each respective line buffer interface unit.

15. The method of claim 10 , further comprising:
receiving, by a line buffer interface unit, a write request from a producer processor;
identifying, by the line buffer interface unit within a line group buffer assigned to the line buffer interface unit and stored by the memory device, a write location corresponding to the write request; and
storing data at the write location within the line group buffer assigned to the line buffer interface unit.

16. The method of claim 15 , further comprising:
receiving, by the line buffer interface unit, a read request from one or more consumer processors;
identifying, by the line buffer interface unit within the line group buffer assigned to the line buffer interface unit and stored by the memory device, a read location corresponding to the read request; and
providing data stored at the read location within the line group buffer assigned to the line buffer interface unit.

17. The method of claim 10 , further comprising:
converting, by translation circuitry of a line buffer interface unit, a read or write request into a linear address within a line group buffer managed by the line buffer interface unit and stored by the memory device.

18. The method of claim 10 , further comprising reassigning a line buffer interface unit to manage a different line group buffer stored by the memory device.

19. The method of claim 18 , further comprising reassigning the line buffe

Assignees

• Google Llc

Inventors

• Desai Neeti
• Meixner Albert
• Zhu Qiuling
• Redgrave Jason Rupert
• Shacham Ofer
• Finchelstein Daniel Frederic

Classifications

• H04N25/701 Primary

  Line sensors · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• H04N5/91

  Television signal processing therefor · CPC title

• H04N5/3692 Primary

  Electricity · mapped topic