Line buffer unit for image processor

Patent metadata

Field	Value
Publication number	US-10638073-B2
Application number	US-201916402310-A
Country	US
Kind code	B2
Filing date	May 3, 2019
Priority date	Apr 23, 2015
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

First claim

The invention claimed is:

1. A device configured to manage a plurality of line group buffers having different respective sizes, the device comprising:
a memory device configured to store line group data; and
a plurality of line buffer interface units,
wherein each line buffer interface unit is assigned to manage read and write requests for a respective line group buffer stored by the memory device, each line group buffer being a respective partition of storage within the memory device,
wherein each line buffer interface unit is configured with configuration parameters that specify a respective size for a respective line group buffer managed by the line buffer interface unit, and
wherein the device is configured to assign multiple line buffer interface units to manage respective line group buffers having different respective sizes.

2. The device of claim 1 , wherein the configuration parameters that specify the respective sizes of line group buffers managed by the line buffer interface units are based on output sizes of respective kernel programs that provide write requests to the line buffer interface units.

3. The device of claim 1 , wherein the configuration parameters that specify the respective sizes of lien group buffers managed by the line buffer interface units are stored in a respective programmable configuration space of each respective line buffer interface unit.

4. The device of claim 1 , wherein each line buffer interface unit is configured to receive a write request from a producer processor, to identify, within a line group buffer assigned to the line buffer interface unit and stored by the memory device, a write location corresponding to the write request, and to store data at the write location within the line group buffer assigned to the line buffer interface unit.

5. The device of claim 4 , wherein each line buffer interface unit is configured to receive a read request from one or more consumer processors, to identify, within the line group buffer assigned to the line buffer interface unit and stored by the memory device, a read location corresponding to the read request, and to provide data stored at the read location within the line group buffer assigned to the line buffer interface unit.

6. The device of claim 1 , wherein each line buffer interface unit has translation circuitry that is configured to convert a read or write request into a linear address within a line group buffer managed by the line buffer interface unit and stored by the memory device.

7. The device of claim 1 , wherein the device is configured to reassign a line buffer interface unit to manage a different line group buffer stored by the memory device.

8. The device of claim 7 , wherein the device is configured to reassign the line buffer interface unit upon the line buffer interface unit handling all outstanding read requests for a previously assigned line group buffer stored by the memory device.

9. The device of claim 1 , further comprising a plurality of stencil processors that are each configured to communicate with respective line buffer interface units to read from and write to one or more of the plurality of line group buffers stored by the memory device.

10. The device of claim 9 , wherein the line buffer interface units are configured to buffer intermediate results of an image processing pipeline within the respective line group buffers stored by the memory device.

11. A method for managing a plurality of line group buffers having different respective sizes, the method being performed by a device comprising a memory device configured to store line group data and a plurality of line buffer interface units, the method comprising:
configuring each line buffer interface unit with respective configuration parameters that assign a respective line group buffer to the line buffer interface unit and that specify a respective size for the respective line group buffer assigned to the line buffer interface unit, each line group buffer being a respective partition of storage within the memory device, including assigning multiple line buffer interface units to manage respective line group buffers having different respective sizes; and
managing, by each line buffer interface unit, read and write requests for a respective line group buffer assigned to the line buffer interface unit.

12. The method of claim 11 , wherein the configuration parameters that specify the respective sizes of line group buffers managed by the line buffer interface units are based on output sizes of respective kernel programs that provide write requests to the line buffer interface units.

13. The method of claim 11 , further comprising storing the configuration parameters that specify the respective sizes of lien group buffers managed by the line buffer interface units in a respective programmable configuration space of each respective line buffer interface unit.

14. The method of claim 11 , further comprising:
receiving, by a line buffer interface unit, a write request from a producer processor;
identifying, by the line buffer interface unit within a line group buffer assigned to the line buffer interface unit and stored by the memory device, a write location corresponding to the write request; and
storing data at the write location within the line group buffer assigned to the line buffer interface unit.

15. The method of claim 14 , further comprising:
receiving, by the line buffer interface unit, a read request from one or more consumer processors;
identifying, by the line buffer interface unit within the line group buffer assigned to the line buffer interface unit and stored by the memory device, a read location corresponding to the read request; and
providing data stored at the read location within the line group buffer assigned to the line buffer interface unit.

16. The method of claim 1 , further comprising:
converting, by translation circuitry of a line buffer interface unit, a read or write request into a linear address within a line group buffer managed by the line buffer interface unit and stored by the memory device.

17. The method of claim 11 , further comprising reassigning a line buffer interface unit to manage a different line group buffer stored by the memory device.

18. The method of claim 17 , further comprising reassigning the line buffer interface unit upon the line buffer interface unit handling all outstanding read requests for a previously assigned line group buffer stored by the memory device.

19. The method of claim 11 , wherein the device comprises a plurality of stencil processors and further comprising:
communicating, by the plurality of stencil processors, with respective line buffer interface units to read from and write to one or more of the plurality of line group buffers stored by the memory device.

20. The method of claim 19 , further comprising buffering, by the line buffer interface units, intermediate results of an image processing pipeline within the respective line group buffers stored by the memory device.

Assignees

• Google Llc

Inventors

• Desai Neeti
• Meixner Albert
• Zhu Qiuling
• Redgrave Jason Rupert
• Shacham Ofer
• Finchelstein Daniel Frederic

Classifications

• H04N5/91

  Television signal processing therefor · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• H04N5/3692 Primary

  Electricity · mapped topic

• H04N25/701 Primary

  Line sensors · CPC title