Energy efficient processor core architecture for image processor

Patent metadata

Field	Value
Publication number	US-11138013-B2
Application number	US-202017001097-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Apr 23, 2015
Publication date	Oct 5, 2021
Grant date	Oct 5, 2021

Abstract

An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

First claim

The invention claimed is:

1. A system comprising:
one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
receiving an input program to be executed on a device comprising:
a plurality of random access memories, and
a plurality of execution lanes, wherein different groups of the execution lanes are assigned to use a different respective random access memory of the plurality of random access memories;

determining that the input program specifies two or more execution lanes in a same group of the plurality of execution lanes to compete for different memory locations in a same random access memory of the plurality of random access memories; and
in response, modifying the input program to generate multiple instructions that cause execution lanes within each group to access a respective random access memory sequentially.

2. The system of claim 1 , wherein the plurality of execution lanes includes a plurality of rows of execution lanes, wherein the different groups of the execution lanes comprise different rows of the execution lanes.

3. The system of claim 1 , wherein the plurality of execution lanes includes a plurality of columns of execution lanes, wherein the different groups of the execution lanes comprise different columns of the execution lanes.

4. The system of claim 1 , wherein the plurality of execution lanes are arranged in an array of execution lanes.

5. The system of claim 4 , wherein the plurality of execution lanes are coupled to a two dimensional shift register array structure, wherein the execution lanes are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array structure.

6. The system of claim 5 , wherein the plurality of random access memories are to store register values that spill out of the two dimensional shift register array structure.

7. The system of claim 1 , wherein the plurality of random access memories are to store look-up table information.

8. The system of claim 1 , wherein each of the multiple instructions cause the execution lanes to read data from the respective random access memory or to write data to the respective random access memory.

9. The system of claim 1 , wherein each execution lane of the plurality of execution lanes comprises a memory unit configured to write data from local register space into random access memory and to write data from random access memory into local register space.

10. The system of claim 1 , wherein the plurality of execution lanes is coupled to a scalar processor to receive and execute the input program in SIMD fashion.

11. The system of claim 1 , wherein the input program is contained in a larger data structure having a VLIW format.

12. A method comprising:
receiving an input program to be executed on a device comprising:
a plurality of random access memories, and
a plurality of execution lanes, wherein different groups of the execution lanes are assigned to use a different respective random access memory of the plurality of random access memories;

determining that the input program specifies two or more execution lanes in a same group of the plurality of execution lanes to compete for different memory locations in a same random access memory of the plurality of random access memories; and
in response, modifying the input program to generate multiple instructions that cause execution lanes within each group to access a respective random access memory sequentially.

13. The method of claim 12 , wherein the plurality of execution lanes includes a plurality of rows of execution lanes, wherein the different groups of the execution lanes comprise different rows of the execution lanes.

14. The method of claim 12 , wherein the plurality of execution lanes includes a plurality of columns of execution lanes, wherein the different groups of the execution lanes comprise different columns of the execution lanes.

15. The method of claim 12 , wherein the plurality of execution lanes are arranged in an array of execution lanes.

16. The method of claim 15 , wherein the plurality of execution lanes are coupled to a two dimensional shift register array structure, wherein the execution lanes are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array structure.

17. The method of claim 16 , wherein the plurality of random access memories are to store register values that spill out of the two dimensional shift register array structure.

18. The method of claim 12 , wherein the plurality of random access memories are to store look-up table information.

19. The method of claim 12 , wherein each of the multiple instructions cause the execution lanes to read data from the respective random access memory or to write data to the respective random access memory.

20. The method of claim 12 , wherein each execution lane of the plurality of execution lanes comprises a memory unit configured to write data from local register space into random access memory and to write data from random access memory into local register space.

Assignees

• Google Llc

Inventors

• Meixner Albert
• Redgrave Jason Rupert
• Shacham Ofer
• Finchelstein Daniel Frederic
• Zhu Qiuling

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• H04N3/14

  by means of electrically scanned solid-state devices (for picture generation H04N25/00) · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title