Image processor with high throughput internal communication protocol

Patent metadata

Field	Value
Publication number	US-10872393-B2
Application number	US-201715595242-A
Country	US
Kind code	B2
Filing date	May 15, 2017
Priority date	May 15, 2017
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.

First claim

The invention claimed is:

1. A processor, comprising:
a network implementing a credit counter protocol that requires each sender to receive an acknowledgement from a receiver for a data packet to be transmitted before the sender sends data units belonging to the data packet;
one or more processing cores coupled to the network; and
a transmitter circuit coupling a first processing core of the one or more processing cores to the network, the transmitter circuit being configured to transmit data units output by the first processing core into the network, the transmitter circuit comprising control logic circuitry that is configured to cause the transmitter circuit to:
initiate transmitting a first data packet to a first receiver of the processor,
provide a request for a different second data packet to be transmitted to a different second receiver of the processor before a last data unit of the first data packet has been transmitted to the first receiver,
receive a pre-issued acknowledgement for the different second data packet to be transmitted before the last data unit of the first data packet has been transmitted to the first receiver,
increment a different second receiver-specific credit counter for the second receiver in response to receiving the pre-issued acknowledgement for the different second data packet to be transmitted,
receive an indication that the last data unit of the first data packet has been consumed by the first receiver,
increment a first receiver-specific credit counter in response to receiving the indication that the last data unit belonging to the first data packet has been consumed by the first receiver, and
send a first data unit belonging to the different second data packet to the different second receiver using credits of the second receiver-specific credit counter incremented due to receiving the pre-issued acknowledgement for the different second data packet to be transmitted.

2. The processor of claim 1 , wherein the control logic circuitry comprises a plurality of credit counters, and wherein the control logic circuitry is configured to reassign each credit counter to a different respective receiver after a respective data packet is transmitted.

3. The processor of claim 1 , wherein the second receiver of the second data packet is a different component of the processor than the first receiver of the first data packet.

4. The processor of claim 1 , wherein the processor further comprises a line buffer, and wherein the first receiver of the first data packet is the line buffer.

5. The processor of claim 1 , wherein receiving the pre-issued transaction acknowledgement for the second data packet comprises receiving the pre-issued acknowledgement for the second data packet before sending any data units of the first data packet.

6. The processor of claim 1 , wherein the control logic circuitry is configured to increment the credits of the second receiver-specific credit counter due to receiving the pre-issued acknowledgment whenever the first receiver of the processor is a different component than the second receiver of the processor.

7. The processor of claim 1 , wherein the control logic circuitry is configured to send interleaved data units to the first receiver of the processor and the second receiver of the processor using the first receiver-specific credit counter for data units belonging to the first data packet and the second receiver-specific credit counter for data units belonging to the second data packet respectively.

8. A method performed by a processor having one or more processing cores and a network implementing a credit counter protocol that requires each sender to receive an acknowledgement from a receiver for a data packet to be transmitted before the sender sends data units belonging to the data packet, the method comprising:
processing, by a first processing core of the one or more processing cores, program code to generate output data to be sent in a first data packet and a different second data packet;
initiating, by a transmitter circuit coupling the first processing core to the network, transmitting the first data packet to a first receiver of the processor;
providing, by the transmitter circuit, a request for the different second data packet to be transmitted to a different second receiver of the processor before a last data unit of the first data packet has been transmitted to the first receiver;
receiving, by the transmitter circuit, a pre-issued acknowledgement for the different second data packet to be transmitted before the last data unit of the first data packet has been transmitted to the first receiver;
incrementing a different second receiver-specific credit counter for the second receiver in response to receiving the pre-issued acknowledgement for the different second data packet to be transmitted;
receiving, by the transmitter circuit, an indication that the last data unit of the first data packet has been consumed by the first receiver;
incrementing a first receiver-specific credit counter in response to receiving the indication that the last data unit belonging to the first data packet has been consumed by the first receiver; and
sending a first data unit belonging to the second data packet to the different second receiver using credits of the second receiver-specific credit counter incremented due to receiving the pre-issued acknowledgement for the second data packet to be transmitted.

9. The method of claim 8 , wherein the transmitter circuit comprises a plurality of credit counters, and further comprising reassigning each credit counter to a different respective receiver after a respective data packet is transmitted.

10. The method of claim 8 , wherein the second receiver of the processor is a different component of the processor than the first receiver of the processor.

11. The method of claim 8 , wherein the processor further comprises a line buffer, and wherein the first receiver is the line buffer.

12. The method of claim 8 , wherein receiving the pre-issued acknowledgement for the second data packet to be transmitted comprises receiving the pre-issued acknowledgement for the second data packet to be transmitted before sending any data units of the first data packet to be transmitted.

13. The method of claim 8 , further comprising incrementing the credits of the second receiver-specific credit counter due to receiving the pre-issued acknowledgment whenever the first receiver of the processor is a different component than the second receiver of the processor.

14. The method of claim 8 , further comprising sending interleaved data units to the first receiver and the second receiver using the first receiver-specific credit counter for data units belonging to the first data packet and the second receiver-specific credit counter for data units belonging to the second data packet respectively.

15. A processor, comprising:
a network implementing a credit counter protocol that requires each sender to receive an acknowledgement from a receiver for a data packet to be transmitted before the sender sends data units belonging to the data packet;
one or more processing cores coupled to the network; and
a transmitter circuit coupling a first processing core of the one or more processing cores to the network, the transmitter circuit being configured to transmit data units output by the first processing core into the network, the transmitter circuit comprising means for:
initiating transmitting a first data packet to a first receiver of the processor,
providing a request for a different second data packet to be transmitted to a different second receiv

Assignees

• Google Llc

Inventors

• Redgrave Jason
• Meixner Albert
• Zhu Qiuling
• Kim Ji
• VASILYEV Artem
• Shacham Ofer

Classifications

• H04L49/9078

  using an external memory or storage device · CPC title

• H04L47/39

  Credit based · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F15/8023

  Two dimensional arrays, e.g. mesh, torus · CPC title

• G06F12/0813

  with a network or matrix configuration · CPC title