Flip-flop circuit with multiple data paths
US-2026095159-A1 · Apr 2, 2026 · US
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Ye Qi patents
Ye Qi is listed as an inventor on 29 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ye Qi |
| Total patents | 29 |
| First publication | Jul 14, 2015 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Flip-flop circuit with glitch protection
US-11496120-B2 · Nov 8, 2022 · US
Low voltage clock swing tolerant sequential circuits for dynamic power savings
US-11424734-B2 · Aug 23, 2022 · US
Flip-Flop Circuit with Glitch Protection
US-2022231673-A1 · Jul 21, 2022 · US
Low power single retention pin flip-flop with balloon latch
US-11336272-B2 · May 17, 2022 · US
Low Power Single Retention Pin Flip-Flop with Balloon Latch
US-2022094340-A1 · Mar 24, 2022 · US
Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Power Savings
US-2021344329-A1 · Nov 4, 2021 · US
Low voltage clock swing tolerant sequential circuits for dynamic power savings
US-11018653-B1 · May 25, 2021 · US
High-speed soft-edge sense-amplifier-based flip-flop
US-10038429-B1 · Jul 31, 2018 · US
Area efficient flip-flop with improved scan hold-margin
US-10033359-B2 · Jul 24, 2018 · US
Recent patents
Latest publications not already listed above.
Method of forming a composite substrate
US-9991414-B2 · Jun 5, 2018 · US
Pulse-generator
US-9979394-B2 · May 22, 2018 · US
Low clock power data-gated flip-flop
US-9966953-B2 · May 8, 2018 · US
Power rail inbound middle of line (MOL) routing
US-9935100-B2 · Apr 3, 2018 · US
Low clock power data-gated flip-flop
US-2017353186-A1 · Dec 7, 2017 · US
Method of forming a composite substrate
US-2017279006-A1 · Sep 28, 2017 · US
Pulse-generator
US-2017237434-A1 · Aug 17, 2017 · US
Circuit techniques for efficient scan hold path design
US-9678154-B2 · Jun 13, 2017 · US
Power rail inbound middle of line (mol) routing
US-2017133365-A1 · May 11, 2017 · US
Area efficient flip-flop with improved scan hold-margin
US-2017117884-A1 · Apr 27, 2017 · US
Method of forming a composite substrate
US-9634181-B2 · Apr 25, 2017 · US
Compact design of scan latch
US-9584121-B2 · Feb 28, 2017 · US
Area-efficient metal-programmable pulse latch design
US-9564881-B2 · Feb 7, 2017 · US
Compact design of scan latch
US-2016365856-A1 · Dec 15, 2016 · US
Area-efficient metal-programmable pulse latch design
US-2016344374-A1 · Nov 24, 2016 · US
Circuit techniques for efficient scan hold path design
US-2016124043-A1 · May 5, 2016 · US
Digital circuit design with semi-continuous diffusion standard cell
US-9190405-B2 · Nov 17, 2015 · US
Digital circuit design with semi-continuous diffusion standard cell
US-2015221639-A1 · Aug 6, 2015 · US
Low overhead hold-violation fixing solution using metal-programable cells
US-9083325-B2 · Jul 14, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 18 |
| Apple Inc | 8 |
| Koninklijke Philips Nv | 2 |
| Gardner Nathan Frederick | 1 |
| Mclaurin Melvin Barker | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H03K3/037 | 15 |
| H03K3/012 | 11 |
| H03K3/0375 | 11 |
| H03K3/35625 | 7 |
| G01R31/318541 | 5 |