Circuit techniques for efficient scan hold path design

Patent metadata

Field	Value
Publication number	US-9678154-B2
Application number	US-201414528554-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Oct 30, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

First claim

What is claimed is:

1. A method for signal delay in a scan path, comprising:
in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage; and
in a functional mode, disabling the delay devices.

2. The method of claim 1 , wherein the second voltage is at least 0.01 volts greater than the first voltage.

3. The method of claim 1 , wherein disabling the delay devices comprises holding an output of the first one of the delay devices at a constant logic state.

4. The method of claim 3 , wherein the first one of the delay devices is also powered by the second voltage, and the constant logic state corresponds to a voltage approximately equal to the second voltage.

5. The method of claim 1 , further comprising generating the first voltage from the second voltage using a diode-connected transistor.

6. The method of claim 5 , wherein the first voltage is approximately equal to the second voltage minus a voltage across the diode-connected transistor.

7. The method of claim 1 , wherein the delay devices are coupled between an output of a first latch and an input of a second latch.

8. The method of claim 7 , further comprising:
inputting the scan signal to an input of the first latch in the scan mode; and
inputting a data signal to the input of the first latch in the functional mode.

9. The method of claim 1 , wherein the first one of the delay devices comprises a NAND gate having a first input and a second input, the scan signal is input to the first input of the NAND gate in the scan mode, and disabling the delay devices in the functional mode comprises inputting a logic zero to the second input of the NAND gate.

10. The method of claim 1 , wherein the first one of the delay devices comprises a NOR gate having a first input and a second input, the scan signal is input to the first input of the NOR gate in the scan mode, and disabling the delay devices in the functional mode comprises inputting a logic one to the second input of the NOR gate.

11. The method of claim 1 , wherein, in the scan mode, the first one of the delay devices has an output voltage swing approximately equal to the first voltage, and the second one of the delay devices has an output voltage swing approximately equal to the second voltage.

12. The method of claim 11 , wherein a third one of the delay devices coupled between the first and second ones of the delay devices outputs a logic zero to an input of the second one of the delay devices in the functional mode.

13. The method of claim 1 , wherein the first voltage is applied across the first one of the delay devices to power the first one of the delay devices, and the second voltage is applied across the second one of the delay devices to power the second one of the delay devices.

14. An apparatus for signal delay in a scan path, comprising:
means for, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage; and
means for, in a functional mode, disabling the delay devices.

15. The apparatus of claim 14 , wherein the second voltage is at least 0.01 volts greater than the first voltage.

16. The apparatus of claim 14 , wherein the means for disabling the delay devices comprises means for holding an output of the first one of the delay devices at a constant logic state.

17. The apparatus of claim 16 , wherein the first one of the delay devices is also powered by the second voltage, and the constant logic state corresponds to a voltage approximately equal to the second voltage.

18. The apparatus of claim 14 , further comprising means for generating the first voltage from the second voltage.

19. The apparatus of claim 14 , wherein the delay devices are coupled between an output of a first latch and an input of a second latch.

20. The apparatus of claim 19 , further comprising:
means for inputting the scan signal to an input of the first latch in the scan mode; and
means for inputting a data signal to the input of the first latch in the functional mode.

21. The apparatus of claim 14 , wherein the first one of the delay devices comprises a NAND gate having a first input and a second input, the scan signal is input to the first input of the NAND gate in the scan mode, and the means for disabling the delay devices in the functional mode comprises means for inputting a logic zero to the second input of the NAND gate.

22. The apparatus of claim 14 , wherein the first one of the delay devices comprises a NOR gate having a first input and a second input, the scan signal is input to the first input of the NOR gate in the scan mode, and disabling the delay devices in the functional mode comprises inputting a logic one to the second input of the NOR gate.

23. The apparatus of claim 14 , wherein, in the scan mode, the first one of the delay devices has an output voltage swing approximately equal to the first voltage, and the second one of the delay devices has an output voltage swing approximately equal to the second voltage.

24. The apparatus of claim 23 , wherein a third one of the delay devices coupled between the first and second ones of the delay devices outputs a logic zero to an input of the second one of the delay devices in the functional mode.

25. The apparatus of claim 14 , wherein the first voltage is applied across the first one of the delay devices to power the first one of the delay devices, and the second voltage is applied across the second one of the delay devices to power the second one of the delay devices.

26. A delay circuit, comprising:
a first delay device having a first input, a second input, and an output, wherein the first delay device is powered by a first voltage;
a second delay device having an input coupled to the output of the first delay device, and an output, wherein the second delay device is powered by the first voltage; and
a third delay device having an input coupled to the output of the second delay device, and an output, wherein the third delay device is powered by a second voltage;
wherein the second voltage is greater than the first voltage, and wherein the first, second and third delay devices are configured to propagate a scan signal from the first input of the first delay device to the output of the third delay device if a first logic state is input to the second input of the first delay device, and to block a signal from propagating through the first, second and third delay devices if a second logic state is input to the second input of the first delay device.

27. The delay circuit of claim 26 , wherein the second voltage is at least 0.01 volts greater than the first voltage.

28. The delay circuit of claim 26 , wherein the first delay device is also powered by the second voltage, and the first delay device is configured to output a voltage approximately equal to the second voltage if the second logic state is input to the second input of the first delay device.

Assignees

• Qualcomm Inc

Inventors

• Datta Animesh
• Ye Qi
• Dillen Steven James

Classifications

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G11C2029/3202

  Scan chain · CPC title

• H03K5/134

  with field-effect transistors · CPC title