Compact design of scan latch

Patent metadata

Field	Value
Publication number	US-9584121-B2
Application number	US-201514736213-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jun 10, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and I C , and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

First claim

What is claimed is:

1. A metal oxide semiconductor (MOS) device, comprising:
a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C, the first latch being configured to output Q, where the output Q is a function of CF, IF, and I C , and the latch feedback F is a function of the output Q;
wherein the latch feedback F is functionally Q , and the output Q is functionally (C +I)F +IC .

2. The MOS device of claim 1 , wherein the first latch comprises a first set of transistors stacked in series, the first set of transistors comprising at least five transistors.

3. The MOS device of claim 2 , wherein the first set of transistors comprises at least three p-type MOS (pMOS) transistors and at least two n-type MOS (nMOS) transistors.

4. The MOS device of claim 2 , wherein each transistor of the first set of transistors is coupled to one of the latch input I, the latch clock C, or an inverse latch clock C .

5. The MOS device of claim 2 , wherein the first latch further comprises a second set of transistors stacked in series, the second set of transistors comprising at least three transistors.

6. The MOS device of claim 5 , wherein the second set of transistors comprises at least two p-type MOS (pMOS) transistors and at least one n-type MOS (nMOS) transistor.

7. The MOS device of claim 5 , wherein each transistor of the second set of transistors is coupled to one of the latch feedback F, or an inverse latch clock C .

8. The MOS device of claim 5 , wherein the first latch further comprises a third set of transistors in parallel, the third set of transistors being stacked in series with the second set of transistors.

9. The MOS device of claim 8 , wherein each transistor of the third set of transistors is coupled to one of the latch input I, or the latch clock C.

10. The MOS device of claim 1 , further comprising a second latch coupled to the first latch, the second latch being configured as a latch in a scan mode and as a pulse latch in a functional mode.

11. The MOS device of claim 10 , wherein the second latch is configured to be clocked with a scan clock in the scan mode and with a pulse clock in the functional mode, the pulse clock being different than the scan clock.

12. The MOS device of claim 10 , wherein the first latch operates as a master latch and the second latch operates as a slave latch during the scan mode.

13. The MOS device of claim 1 , wherein the first latch has a width of at least eight grids including at least eight gate interconnects that extend across the device.

14. The MOS device of claim 13 , wherein each of at least five gate interconnects of the at least eight gate interconnects is shared between one p-type MOS (pMOS) transistor and one n-type MOS (nMOS) transistor.

15. A metal oxide semiconductor (MOS) device, comprising:
a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C, the first latch being configured to output Q, where the output Q is a function of CF, IF, and I C , and the latch feedback F is a function of the output Q, and
wherein the first latch comprises:
a first p-type MOS (pMOS) transistor having a first pMOS transistor source, a first pMOS transistor gate, and a first pMOS transistor drain, the first pMOS transistor gate being coupled to the latch input I;
a second pMOS transistor having a second pMOS transistor source, a second pMOS transistor gate, and a second pMOS transistor drain, the second pMOS transistor gate being coupled to an inverse latch clock C , the second pMOS transistor source being coupled to the first pMOS transistor source, the second pMOS transistor drain being coupled to the first pMOS transistor drain;
a first n-type MOS (nMOS) transistor having a first nMOS transistor source, a first nMOS transistor gate, and a first nMOS transistor drain, the first nMOS transistor drain being coupled to the first pMOS transistor drain and the second pMOS transistor drain; and
a second nMOS transistor having a second nMOS transistor source, a second nMOS transistor gate, and a second nMOS transistor drain, the second nMOS transistor drain being coupled to the first nMOS transistor source, the second nMOS transistor source being coupled to a first voltage source,
wherein the first nMOS transistor gate is coupled to one of the latch input I or the inverse latch clock C , and the second nMOS transistor gate is coupled to an other one of the latch input I or the inverse latch clock C .

16. The MOS device of claim 15 , wherein the first latch further comprises:
a third pMOS transistor having a third pMOS transistor source, a third pMOS transistor gate, and a third pMOS transistor drain, the third pMOS transistor source being coupled to a second voltage source; and
a fourth pMOS transistor having a fourth pMOS transistor source, a fourth pMOS transistor gate, and a fourth pMOS transistor drain, the fourth pMOS transistor source being coupled to the third pMOS transistor drain, the fourth pMOS transistor drain being coupled to the first pMOS transistor source and the second pMOS transistor source,
wherein the third pMOS transistor gate is coupled to one of the latch input I or the latch clock C, and the fourth pMOS transistor gate is coupled to an other one of the latch input I or the latch clock C.

17. The MOS device of claim 16 , wherein the first latch further comprises:
a third nMOS transistor having a third nMOS transistor source, a third nMOS transistor gate, and a third nMOS transistor drain, the third nMOS transistor source being coupled to the first voltage source, the third nMOS transistor gate being coupled to the latch input I; and
a fourth nMOS transistor having a fourth nMOS transistor source, a fourth nMOS transistor gate, and a fourth nMOS transistor drain, the fourth nMOS transistor source being coupled to the first voltage source, the fourth nMOS transistor drain being coupled to the third nMOS transistor drain, the fourth nMOS transistor gate being coupled to the latch clock C.

18. The MOS device of claim 17 , wherein the first latch further comprises:
a fifth pMOS transistor having a fifth pMOS transistor source, a fifth pMOS transistor gate, and a fifth pMOS transistor drain, the fifth pMOS transistor source being coupled to the second voltage source, the fifth pMOS transistor drain being coupled to the first pMOS transistor source and the second pMOS transistor source, the fifth pMOS transistor gate being coupled to the latch feedback F; and
a fifth nMOS transistor having a fifth nMOS transistor source, a fifth nMOS transistor gate, and a fifth nMOS transistor drain, the fifth nMOS transistor source being coupled to the third nMOS transistor drain and the fourth nMOS transistor drain, the fifth nMOS transistor drain being coupled to the first pMOS transistor drain and the second pMOS transistor drain, the fifth nMOS transistor gate being coupled to the latch feedback F.

19. The MOS device of claim 18 , wherein the first latch further comprises a NAND gate with a first NAND gate input, a second NAND gate input, and a NAND gate output, wherein:
the first NAND gate input is coupled to the first pMOS transistor drain, the second pMOS transistor drain, the first nMOS transistor drain, and the fifth nMOS transistor drain;
the second NAND gate input is coupled to a shift input; and
the NAND gate output is the latch feedback F.

20. The MOS device of claim 18 , wherein the first latch further comprises an inverter with an inverter input

Assignees

• Qualcomm Inc

Inventors

• Ye Qi
• Duan Zhengyu
• Dillen Steven James
• Datta Animesh

Classifications

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H03K3/35625

  using complementary field-effect transistors · CPC title

• G01R31/318541

  Scan latches or cell details · CPC title

• H03K3/037 Primary

  Bistable circuits · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title