Pulse-generator

Patent metadata

Field	Value
Publication number	US-9979394-B2
Application number	US-201615044988-A
Country	US
Kind code	B2
Filing date	Feb 16, 2016
Priority date	Feb 16, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

First claim

What is claimed is:

1. A pulse generator comprising:
a first latch configured to store a first state or a second state, the first latch having a first latch data input, one of a set input or a reset input, a first pulse clock input, and a first latch output, the first data latch input being coupled to a fixed logic value, wherein the fixed logic value is a logical low, and the first latch has the set input coupled to a clock signal, said one of the set input or the reset input being coupled to the clock signal or an inverted clock signal, respectively, the first latch comprising:
a first inverter having a first inverter input and a first inverter output;
a transmission gate gated by the pulse clock and an inverted pulse clock, the transmission gate having a transmission gate input and a transmission gate output, the transmission gate input being coupled to the first inverter output;
a NAND gate having a first NAND gate input, a second NAND gate input, and a NAND gate output, the first NAND gate input being coupled to the transmission gate output, the second NAND gate input being coupled to the set input, the NAND gate output being the first latch output; and
a tri-state inverter having a tri-state inverter input and a tri-state inverter output, the tri-state inverter being gated by the pulse clock and the inverted pulse clock, the NAND gate output being coupled to the tri-state inverter input, the tri-state inverter output being coupled to the first NAND gate input; and
an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output, the clock signal being coupled to the first AND gate input, the first latch output being coupled to the second AND gate input, the AND gate output being configured to output a pulsed clock, the pulsed clock being coupled to the first pulse clock input.

2. The pulse generator of claim 1 , further comprising an inverter having an inverter input and an inverter output, the inverter input being coupled to the AND gate output, the inverter output being the inverted pulse clock.

3. The pulse generator of claim 2 , wherein the first latch has a first inverted pulse clock input coupled to the inverted pulse clock.

4. A method of pulse generation comprising:
generating an edge of a pulse based on an edge of a clock signal, the pulse having a logical value after the edge; and
maintaining the pulse at the logical value after the edge based on a propagation of a signal through a circuit, wherein the circuit is a type of circuit that is being clocked by the pulse, and wherein maintaining the pulse at the logical value after the edge based on the propagation of the signal through the circuit includes sampling a fixed logic value on a data input of a latch of the circuit and providing feedback within the circuit through a NAND gate and a tri-state inverter, the circuit including the NAND gate and the tri-state inverter.

5. The method of claim 4 , wherein the edge of the pulse comprises a rising edge and the logical value of the pulse after the rising edge comprises a logical high value.

6. The method of claim 5 , wherein the edge of the clock signal comprises a rising edge of the clock signal, the edge of the pulse based on the rising edge of the clock signal.

7. The method of claim 6 , wherein maintaining the pulse at the logical value after the edge based on the propagation of the signal through the circuit includes generating a falling edge of the pulse based on an output of a first latch.

8. A pulse generator comprising:
means for generating an edge of a pulse based on an edge of a clock signal, the pulse having a logical value after the edge; and
means for maintaining the pulse at the logical value after the edge based on a propagation of a signal through a circuit, and wherein the means for maintaining the pulse at the logical value after the edge based on the propagation of the signal through the circuit includes a first latch configured to store a first state or a second state of the signal, the first latch having a first data latch input, a set input, a first pulse clock input, and a first latch output, the first data latch input being coupled to a fixed logic value, the set input being coupled to the clock signal, the first latch further comprising:
a first inverter having a first inverter input and a first inverter output;
a transmission gate gated by a pulse clock and an inverted pulse clock, the transmission gate having a transmission gate input and a transmission gate output, the transmission gate input being coupled to the first inverter output;
a NAND gate having a first NAND gate input, a second NAND gate input, and a NAND gate output, the first NAND gate input being coupled to the transmission gate output, the second NAND gate input being coupled to the set input, the NAND gate output being the first latch output; and

a tri-state inverter having a tri-state inverter input and a tri-state inverter output, the tri-state inverter being gated by the pulse clock and the inverted pulse clock, the NAND gate output being coupled to the tri-state inverter input, the tri-state inverter output being coupled to the first NAND gate input.

9. The pulse generator of claim 8 , wherein the edge of the pulse comprises a rising edge and the logical value of the pulse after the rising edge comprises a logical high value.

10. The pulse generator of claim 9 , wherein the edge of the clock signal comprises a rising edge of the clock signal, the edge of the pulse based on the rising edge of the clock signal.

11. The pulse generator of claim 10 , wherein maintaining the pulse at the logical value after the edge based on the propagation of the signal through the circuit includes generating a falling edge of the pulse based on an output of a first latch.

12. The pulse generator of claim 8 , wherein the means for generating an edge of a pulse based on an edge of a clock signal includes an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output, the clock signal being coupled to the first AND gate input.

13. A pulse generator comprising:
a first circuit configured to generate an edge of a pulse based on an edge of a clock signal, the pulse having a logical value after the edge; and
the first circuit further configured to maintain the pulse at the logical value after the edge based on a propagation of a signal through a circuit the circuit including the first circuit, the signal comprising a data signal propagating through the circuit, and wherein the first circuit includes an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output, the clock signal being coupled to the first AND gate input and wherein the first circuit further includes a first latch configured to store a first state or a second state, the first latch having a first latch data input, a set input, a first pulse clock input, and a first latch output, the first latch data input being coupled to a fixed logic value, the set input being coupled to the clock signal, the first latch further comprising:
a first inverter having a first inverter input and a first inverter output;
a transmission gate gated by a pulse clock and an inverted pulse clock, the transmission gate having a transmission gate input and a transmission gate output, the transmission gate input being coupled to the first inverter output;
a NAND gate having a first NAND gate input, a second NAND gate input, and a NAND gate output, the first NAND gate input being coupled to the transmission gate output, the second NAND gate input being coupled to the set input, the NAND gate output being the first latch output; and

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Assignees

• Qualcomm Inc

Inventors

• Ye Qi
• Datta Animesh
• Narayanan Venkatasubramanian
• Boynapalli Venugopal

Classifications

• H03K3/033

  Monostable circuits · CPC title

• H03K19/00384 Primary

  in field effect transistor circuits · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K5/04

  by increasing duration; by decreasing duration · CPC title