Geometric mask rule check with favorable and unfavorable zones
US-2025298957-A1 · Sep 25, 2025 · US
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Wu Ping-Chieh patents
Wu Ping-Chieh is listed as an inventor on 37 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wu Ping-Chieh |
| Total patents | 37 |
| First publication | Feb 10, 2015 |
| Latest publication | Sep 25, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Geometric mask rule check with favorable and unfavorable zones
US-12406130-B2 · Sep 2, 2025 · US
Method for coloring circuit layout and system for performing the same
US-12159092-B2 · Dec 3, 2024 · US
Geometric mask rule check with favorable and unfavorable zones
US-2024311545-A1 · Sep 19, 2024 · US
Geometric mask rule check with favorable and unfavorable zones
US-12019974-B2 · Jun 25, 2024 · US
Method for coloring circuit layout and system for performing the same
US-2023367942-A1 · Nov 16, 2023 · US
Method for coloring circuit layout and system for performing the same
US-11790145-B2 · Oct 17, 2023 · US
Geometric Mask Rule Check With Favorable and Unfavorable Zones
US-2023325579-A1 · Oct 12, 2023 · US
Geometric mask rule check with favorable and unfavorable zones
US-11714951-B2 · Aug 1, 2023 · US
Method of manufacturing semiconductor devices and pattern formation method for manufacturing semiconductor devices
US-2023005738-A1 · Jan 5, 2023 · US
Recent patents
Latest publications not already listed above.
Geometric Mask Rule Check With Favorable and Unfavorable Zones
US-2022365419-A1 · Nov 17, 2022 · US
Method for coloring circuit layout and system for performing the same
US-2022335192-A1 · Oct 20, 2022 · US
Method for coloring circuit layout and system for performing the same
US-11392742-B2 · Jul 19, 2022 · US
Method for coloring circuit layout and system for performing the same
US-2021019464-A1 · Jan 21, 2021 · US
Methodology for pattern density optimization
US-10860774-B2 · Dec 8, 2020 · US
Method for coloring circuit layout and system for performing the same
US-10796055-B2 · Oct 6, 2020 · US
Method for integrated circuit manufacturing
US-10747938-B2 · Aug 18, 2020 · US
Method for coloring circuit layout and system for performing the same
US-2020050725-A1 · Feb 13, 2020 · US
Method for coloring circuit layout and system for performing the same
US-10509881-B2 · Dec 17, 2019 · US
Method for Integrated Circuit Manufacturing
US-2019340330-A1 · Nov 7, 2019 · US
Method for integrated circuit manufacturing
US-10360339-B2 · Jul 23, 2019 · US
Method for coloring circuit layout and system for performing the same
US-2019095569-A1 · Mar 28, 2019 · US
Methodology for pattern density optimization
US-2018349545-A1 · Dec 6, 2018 · US
Methodology for pattern density optimization
US-10049178-B2 · Aug 14, 2018 · US
Methodology for pattern density optimization
US-2016275232-A1 · Sep 22, 2016 · US
Methodology for pattern density optimization
US-9411924-B2 · Aug 9, 2016 · US
Method for Integrated Circuit Manufacturing
US-2016162627-A1 · Jun 9, 2016 · US
Method for integrated circuit manufacturing
US-9262578-B2 · Feb 16, 2016 · US
Chip level critical point analysis with manufacturer specific data
US-9189587-B2 · Nov 17, 2015 · US
Method for Integrated Circuit Manufacturing
US-2015310158-A1 · Oct 29, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 28 |
| Taiwan Semiconductor Mfg | 8 |
| Taiwan Semiconductor Mfg Co Ltd | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G03F1/36 | 23 |
| G06F30/398 | 23 |
| G06F30/39 | 16 |
| G06F17/5081 | 13 |
| G03F1/70 | 11 |