Method for coloring circuit layout and system for performing the same

Patent metadata

Field	Value
Publication number	US-11790145-B2
Application number	US-202217853758-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Sep 28, 2017
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

First claim

What is claimed is:

1. A mask data generation apparatus, comprising:
a non-transitory computer-readable memory storing a program; and
a processor operatively coupled with the memory,
wherein the program, when executed by the processor, causes the processor to perform:
receiving a multiple-patterning technology (MPT)-compliant circuit layout having a plurality of nodes, each node representing a circuit pattern;
assigning a number to an analysis counter;
identifying nodes being separated by a distance less than a minimum separation distance as target networks, the target networks being presented in an imaginary X-Y coordinate plane;
identifying a first node in each target network using a coordinate-based method;
assigning a first feature to the first node in each target network;
assigning the first feature and a second feature to remaining nodes in the target networks in an alternating manner so that any two immediately adjacent nodes in the target network have different features;
updating the analysis counter; and
analyzing the MPT-compliant circuit layout based on the analysis counter.

2. The mask data generation apparatus of claim 1 , wherein the minimum separation distance is about 70 nm to about 120 nm.

3. The mask data generation apparatus of claim 1 , wherein the first node has a lowest X coordinate and a lowest Y coordinate.

4. The mask data generation apparatus of claim 1 , wherein the first node has a lowest X coordinate and a largest Y coordinate.

5. The mask data generation apparatus of claim 1 , wherein the first node has a largest X coordinate and a lowest Y coordinate.

6. The mask data generation apparatus of claim 1 , wherein the first node has a largest X coordinate and a largest Y coordinate.

7. The mask data generation apparatus of claim 1 , wherein the program, when executed by the processor, further causes the processor to perform:
storing one or more target networks having a unique coloring combination in a storage medium;
identifying networks in a different circuit layout or different regions of the same circuit layout having an arrangement of nodes identical or similar to the stored target networks; and
assigning the unique coloring combination to the identified networks.

8. The mask data generation apparatus of claim 1 , wherein the first feature comprises a first color, and the second feature comprises a second color.

9. The mask data generation apparatus of claim 1 , wherein the first feature comprises a first shape, and the second feature comprises a second shape.

10. The mask data generation apparatus of claim 1 , wherein the first feature comprises a first number, and the second feature comprises a second number.

11. The mask data generation apparatus of claim 1 , wherein the first feature comprises a first icon, and the second feature comprises a second icon.

12. The mask data generation apparatus of claim 1 , wherein the first feature comprises a first symbol, and the second feature comprises a second symbol.

13. A mask data generation apparatus, comprising:
a non-transitory computer-readable memory storing a program; and
a processor operatively coupled with the memory,
wherein the program, when executed by the processor, causes the processor to perform:
receiving a multiple-patterning technology (MPT)-compliant circuit layout having a plurality of nodes, each node representing a circuit pattern;
identifying nodes being separated by a distance less than a minimum separation distance as target networks, the target networks being presented in an imaginary X-Y coordinate plane;
identifying a first node in each target network using a coordinate-based method;
assigning a first feature to the first node in each target network; and
assigning the first feature and a second feature to remaining nodes in the target networks in an alternating manner so that any two immediately adjacent nodes in the target network have different features.

14. The mask data generation apparatus of claim 13 , wherein the minimum separation distance is about 70 nm to about 120 nm.

15. The mask data generation apparatus of claim 13 , wherein the first node has a lowest X coordinate and a lowest Y coordinate.

16. The mask data generation apparatus of claim 13 , wherein the first node has a lowest X coordinate and a largest Y coordinate.

17. The mask data generation apparatus of claim 13 , wherein the first node has a largest X coordinate and a lowest Y coordinate.

18. The mask data generation apparatus of claim 13 , wherein the first node has a largest X coordinate and a largest Y coordinate.

19. The mask data generation apparatus of claim 13 , wherein the first and second features are selected from the group consisting of colors, shapes, numbers, icons, and symbols.

20. A mask data generation apparatus, comprising:
a non-transitory computer-readable memory storing a program and a design rule checker; and
a processor operatively coupled with the memory,
wherein the program, when executed by the processor, causes the processor to receive data from the design rule checker to:
(i) assign a number to an analysis counter;
(ii) identify a first node in a G0-linked network using a coordinate-based method, the G0-linked network being presented in an imaginary X-Y coordinate plane in the computer;
(iii) assign a first feature to the identified first node in the G0-linked network; and
(iv) assign the first feature and a second feature to remaining nodes in the G0-linked network in an alternating manner,
(v) update the analysis counter until any two immediately adjacent linked nodes in a target network have different features, and
analyze the design rule checker based on the analysis counter.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Chia-Ping
• Chih Ming-Hui
• Hsu Chih-Wei
• Wu Ping-Chieh
• Chang ya-ting
• Wang Tsung-Yu
• Cheng Wen-Li
• Yin Hui En
• Huang Wen-Chun
• Liu Ru-Gun
• Gau Tsai-Sheng

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G03F7/70466

  Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title