Methodology for pattern density optimization

Patent metadata

Field	Value
Publication number	US-2016275232-A1
Application number	US-201615170026-A
Country	US
Kind code	A1
Filing date	Jun 1, 2016
Priority date	Oct 11, 2013
Publication date	Sep 22, 2016
Grant date	—

Abstract

The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

First claim

What is claimed is:

1 . A method of data preparation, comprising:
performing an initial data preparation process on an IC design comprising a graphical representation of a layout used to fabricate an integrated chip, wherein the initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design; identifying one or more low-pattern-density areas of the modified IC design using a local density checking element; and adding one or more dummy shapes within the one or more low-pattern-density areas using a dummy shape insertion element, wherein the one or more dummy shapes are separated from the modified shapes by a non-zero space.

2 . The method of claim 1 , wherein the initial data preparation process adds one or more assist features within the IC design, wherein the one or more assist features are directly connected to the shapes.

3 . The method of claim 1 , wherein the initial data preparation process removes a portion of a shape of the IC design along an inside corner arranged between perpendicular edges of the shape.

4 . The method of claim 1 , wherein the modified shapes represent a metal interconnect layer to be formed on the integrated chip.

5 . The method of claim 1 , further comprising:
performing a second data preparation process on the modified IC design that modifies shapes of the one or more dummy shapes using the data preparation element.

6 . The method of claim 5 , further comprising:
adding one or more additional dummy shapes in the modified IC design at positions outside of the low-pattern-density areas after performing the second data preparation process.

7 . The method of claim 1 , wherein the one or more low-pattern-density areas respectively comprise a subset of the IC modified design.

8 . The method of claim 1 , wherein the one or more low-pattern-density areas respectively have a pattern density that results in a processing failure after performing the initial data preparation process.

9 . The method of claim 1 ,
wherein the shapes within the IC design comprise a first shape separated from a second shape by a non-zero space; and wherein the modified shapes of the modified IC design are modified forms of the first shape or the second shape that are separated by at least one of the one or more dummy shapes.

10 . A method of data preparation, comprising:
forming an integrated chip (IC) design used to fabricate an integrated chip using a computation element, wherein the IC design comprises a graphical representation of a layout having a plurality of shapes; performing a first data preparation process that modifies one or more of the plurality of shapes, using a data preparation element; adding a plurality of dummy shapes to the IC design using a dummy shape insertion element, wherein the plurality of dummy shapes are separated from the plurality of shapes by a non-zero space; and performing a second data preparation process, after performing the first data preparation process, which modifies the plurality of dummy shapes using the data preparation element.

11 . The method of claim 10 , wherein the first data preparation process adds one or more assist features within the IC design, wherein the one or more assist features are directly connected to the shapes.

12 . The method of claim 10 , wherein the first data preparation process removes a portion of a shape of the IC design along an inside corner arranged between perpendicular edges of the shape.

13 . The method of claim 10 , wherein the shapes represent a metal interconnect layer to be formed on the integrated chip.

14 . The method of claim 10 , wherein the first data preparation process generates a modified IC design having modified shapes that are modified forms of shapes within the IC design.

15 . The method of claim 14 , further comprising:
identifying one or more low-pattern-density areas of the modified IC design using a local density checking element; adding the plurality of dummy shapes within the one or more low-pattern-density areas; and wherein the first data preparation process is performed on the IC design prior to identifying the one or more low-pattern-density areas.

16 . The method of claim 15 , further comprising:
adding one or more additional dummy shapes in the IC design at positions outside of the low-pattern-density areas after performing the second data preparation process.

17 . The method of claim 15 , wherein the one or more low-pattern-density areas respectively have a pattern density that results in a processing failure after performing the first data preparation process.

18 . The method of claim 14 ,
wherein the IC design has a first shape separated from a second shape by a non-zero space; and wherein the modified shapes are modified forms of the first shape or the second shape that are separated by one or more of the plurality of dummy shapes.

19 . An EDA (Electronic design automation) tool, comprising:
a design tool configured to form an integrated chip (IC) design comprising a graphical representation of an integrated chip having a plurality of shapes; a dummy shape insertion element configured add a plurality of dummy shapes within the IC design, wherein the plurality of dummy shapes are separated from the plurality of shapes by a non-zero space; and a data preparation element configured to perform a first data preparation process that modifies one or more of the plurality of shapes, and to perform a second data preparation process, after performing the first data preparation process, which modifies the plurality of dummy shapes.

20 . The EDA tool of claim 19 , further comprising:
a local density checking element configured to identify one or more low-pattern-density areas of the IC design, wherein respective low-pattern-density areas comprise a subset of the IC design; and wherein the dummy shape insertion element is configured to add the plurality of dummy shapes to the one or more low-pattern-density areas of the IC design.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Hung-Chun
• Chih Ming-Hui
• Wu Ping-Chieh
• Wu Chun-Hung
• Liu Wen-Hao
• Huang Cheng-Hsuan
• Tsai Cheng-Kun
• Huang Wen-Chun
• Liu Ru-Gun

Classifications

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic