Method for integrated circuit manufacturing

Patent metadata

Field	Value
Publication number	US-10360339-B2
Application number	US-201615043961-A
Country	US
Kind code	B2
Filing date	Feb 15, 2016
Priority date	Apr 25, 2014
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

First claim

What is claimed is:

1. A method comprising:
receiving an integrated circuit (IC) design layout, wherein the IC design layout includes multiple IC regions arranged in rows and columns, each of the IC regions defines an IC die, and each of the IC regions includes an initial IC pattern that is substantially identical among the multiple IC regions;
identifying a group of IC regions from the multiple IC regions, wherein all IC regions in the group have a substantially same location effect, wherein said location effect is introduced by global locations of the IC regions on the IC design layout;
after the identifying, performing a correction process to a first IC region in the group, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction;
replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern; and
fabricating a photomask with the IC design layout.

2. The method of claim 1 , further comprising, replacing the initial IC pattern in all other IC regions in the group with the first corrected IC pattern before the fabricating of the photomask.

3. The method of claim 2 , wherein the identifying includes:
comparing location effect of the first and second IC regions at corresponding points of interest of the first and second IC regions; and
treating the first and second IC regions as having a substantially same location effect if location effect difference at each of the corresponding points of interest is within a respective threshold.

4. The method of claim 3 , wherein the points of interest include pixels, target points, segments, polygons, patterns, or areas.

5. The method of claim 3 , wherein a first portion of the points of interest is assigned a different threshold than a second portion of the points of interest.

6. The method of claim 3 , wherein all of the points of interest are assigned a same threshold.

7. The method of claim 1 , wherein the correction process further includes proximity effect correction.

8. The method of claim 1 , further comprising:
repeating the identifying, the performing, and the replacing for other IC regions outside the group before the fabricating of the photomask.

9. The method of claim 1 , wherein the first and second IC regions include other IC patterns, and wherein the performing of the correction process includes modifying all IC patterns in the first IC region, further comprising:
replacing IC patterns in the second IC region with the modified IC patterns in the first IC region.

10. A method comprising:
receiving an integrated circuit (IC) design layout, wherein the IC design layout includes multiple IC regions arranged in rows and columns in the IC design layout, each of the IC regions defines an IC die that includes a same IC pattern;
identifying a group of IC regions from the IC regions, wherein all IC regions in the group have substantially same location effect, wherein the location effect is associated with the global location of the IC pattern in the IC design layout;
performing a correction process to a first IC region of the group, thereby modifying the IC pattern in the first IC region to result in a first corrected IC pattern, wherein the correction process includes location effect correction;
replacing the IC pattern in other IC regions of the group with the first corrected IC pattern; and
fabricating a photomask with the IC design layout.

11. The method of claim 10 , wherein the identifying of the group of IC regions includes:
placing one of the IC regions into the group;
comparing location effect of the one of the IC regions with that of another one of the IC regions to derive a first difference in location effect; and
if the first difference is within a threshold, placing the another one of the IC regions into the group.

12. The method of claim 11 , wherein the comparing includes:
calculating differences in location effect at corresponding points of interest of the one of the IC regions and the another one of the IC regions.

13. The method of claim 12 , wherein the points of interest include pixels, target points, segments, polygons, patterns, areas, or combinations thereof.

14. The method of claim 12 , wherein the first difference is a maximum value among the differences.

15. The method of claim 10 , further comprising, before the fabricating of the photomask:
identifying another group of IC regions from the IC regions, wherein all IC regions in the another group have substantially same location effect which is not substantially same as the location effect in the IC regions of the group.

16. A method comprising:
receiving an integrated circuit (IC) design layout, wherein the IC design layout includes multiple IC regions, each of the IC regions defines an IC die, and each of the IC regions includes an initial IC pattern;
dividing the IC regions into groups based on a location effect analysis to the IC design layout such that IC regions in a same group have a substantially same location effect, wherein said location effect is introduced by global locations of the IC regions on the IC design layout;
performing a correction process to an IC region of one of the groups, wherein the correction process includes location effect correction, and wherein the correction process modifies the initial IC pattern in the IC region to be a corrected IC pattern;
replacing the initial IC pattern in other IC regions of the one of the groups with the corrected IC pattern; and
fabricating a photomask with the IC design layout.

17. The method of claim 16 , further comprising, before the fabricating of the photomask:
repeating the performing of the correction process and the replacing of the initial IC pattern to other ones of the groups.

18. The method of claim 16 , wherein the location effect analysis includes:
comparing location effect of two IC regions at corresponding points of interest of the two IC regions; and
treating the two IC regions as having substantially same location effect if location effect difference at each of the corresponding points of interest is within a respective threshold.

19. The method of claim 18 , wherein the points of interest include pixels, target points, segments, polygons, patterns, or areas.

20. The method of claim 18 , wherein a first portion of the points of interest is assigned a different threshold than a second portion of the points of interest.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Hung-Chun
• Chang Ching-Hsu
• Wu Chun-Hung
• Tsai Cheng Kun
• Chang Feng-Ju
• Lin Feng-Lung
• Wu Ming-Hsuan
• Wu Ping-Chieh
• Liu Ru-Gun
• Huang Wen-Chun
• Liu Wen-Hao

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G03F7/70441 Primary

  Optical proximity correction [OPC] · CPC title

• G03F1/36

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title