Methodology for pattern density optimization

Patent metadata

Field	Value
Publication number	US-9411924-B2
Application number	US-201314051549-A
Country	US
Kind code	B2
Filing date	Oct 11, 2013
Priority date	Oct 11, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.

First claim

What is claimed is:

1. A method for pattern density optimization, comprising:
forming an integrated chip (IC) design comprising a graphical representation of a layout used to fabricate an integrated chip, using a computation element;
performing an initial data preparation process on the IC design, using a data preparation element, to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design;
identifying one or more low-pattern-density areas of the modified IC design having a pattern density that results in a processing failure after performing the initial data preparation process using a local density checking element, wherein respective low-pattern-density areas comprise a subset of the IC modified design;
adjusting the pattern density of the modified IC design within the one or more low-pattern-density areas by adding one or more dummy shapes within the one or more low-pattern-density areas using a dummy shape insertion element, wherein the one or more dummy shapes are separated from the modified shapes by a non-zero space; and
performing a second data preparation process on the modified IC design that modifies shapes of the one or more dummy shapes within the one or more low-pattern-density areas using the data preparation element.

2. The method of claim 1 , further comprising:
performing a pattern recognition or pattern matching process that compares portions of the modified IC design to a predetermined library of patterns to identify predetermined patterns within the modified IC design that are associated with the one or more low-pattern-density areas.

3. The method of claim 2 , further comprising:
adding a number of dummy shapes into the one or more low-pattern-density areas, which varies depending on a pattern identified by the pattern recognition or the pattern matching process.

4. The method of claim 1 , further comprising:
placing a reference layer within the modified IC design that indicates locations of the low-pattern-density areas of the modified IC design.

5. The method of claim 4 , wherein the reference layer is placed in the low-pattern-density areas that have a pattern density below a predetermined threshold value.

6. The method of claim 1 , wherein the initial data preparation process comprises adding one or more assist features directly connected to the shapes within the IC design.

7. The method of claim 6 , wherein the second data preparation process and the initial data preparation process comprise one or more of a data pretreatment that modifies the IC design by modeling the IC design, optical proximity correction (OPC), or a logic operation.

8. The method of claim 1 , further comprising:
adding one or more additional dummy shapes in the modified IC design at positions outside of the low-pattern-density areas; and
performing a concluding data preparation process on the modified IC design after adding the one or more additional dummy shapes.

9. A method for pattern density optimization, comprising:
forming an integrated chip (IC) design comprising a graphical representation of a layout used to fabricate an integrated chip, using a computation element;
performing an initial data preparation process to generate a modified IC design having one or more modified shapes by adding one or more assist features directly connected to shapes within the IC design using a data preparation element, wherein the one or more modified shapes correspond to metal interconnect shapes;
identifying one or more low-pattern-density areas of the modified IC design having a pattern density below a pre-determined threshold value after performing the initial data preparation process using a local density checking element, wherein respective low-pattern-density areas comprise a subset of the modified IC design;
adjusting the pattern density within the one or more low-pattern-density areas by adding one or more dummy shapes within the one or more low-pattern-density areas without adding dummy shapes outside of the one or more low-pattern-density areas using a dummy shape insertion element; and
performing a second data preparation process on the modified IC design that modifies shapes of the one or more dummy shapes within the one or more low-pattern-density areas using the data preparation element.

10. The method of claim 9 , further comprising:
performing a pattern recognition or pattern matching process that compares portions of the modified IC design to a predetermined library of patterns to identify predetermined patterns within the modified IC design that are associated with the one or more low-pattern-density areas.

11. The method of claim 10 , further comprising:
adding a number of dummy shapes into the one or more low-pattern-density areas, which varies depending on a pattern identified by the pattern recognition or the pattern matching process.

12. The method of claim 9 , further comprising:
placing a reference layer over a part of the IC design, wherein the reference layer indicates that locations of the IC design covered by the reference layer are the low-pattern-density areas of the modified IC design.

13. The method of claim 9 , wherein the second data preparation process and the initial data preparation process comprise one or more of a data pretreatment that modifies the IC design by modeling the IC design, optical proximity correction (OPC), or a logic operation.

14. The method of claim 9 , further comprising:
adding one or more additional dummy shapes in the modified IC design at positions outside of the low-pattern-density areas; and
performing a concluding data preparation process on the modified IC design after adding the one or more additional dummy shapes.

15. The method of claim 9 ,
wherein the integrated chip (IC) design has a first shape separated from a second shape by a non-zero space; and
wherein the one or more modified shapes are modified forms of the first shape or the second shape that are separated by at least one of the one or more dummy shapes, which is arranged therebetween.

16. The method of claim 9 , wherein the one or more dummy shapes are separated from the one or more modified shapes by a non-zero space.

17. An EDA (Electronic design automation) tool, comprising:
a design tool configured to form an integrated chip (IC) design, comprising a graphical representation of a layout used to fabricate an integrated chip;
a local density checking element configured to identify one or more low-pattern-density areas of a modified IC design having a pattern density that results in a processing failure, wherein respective low-pattern-density areas comprise a subset of the modified IC design;
a dummy shape insertion element configured to adjust the pattern density of the modified IC design within the one or more low-pattern-density areas by adding one or more dummy shapes within the one or more low-pattern-density areas;
a data preparation element configured to perform an initial data preparation process on the IC design to generate the modified IC design having modified shapes that are modified forms of shapes within the IC design prior to identifying the one or more low-pattern-density areas, and to further perform a second data preparation process on the IC design that modifies shapes of the one or more dummy shapes within the one or more low-pattern-density areas; and
wherein the one or more dummy shapes are separated from the modified shapes by a non-zero space.

18. The EDA tool of claim 17 , wherein the local density checking element is configured to

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Hung-Chun
• Chih Ming-Hui
• Wu Ping-Chieh
• Wu Chun-Hung
• Liu Wen-Hao
• Huang Cheng-Hsuan
• Tsai Cheng-Kun
• Huang Wen-Chun
• Liu Ru-Gun

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F17/5081 Primary

  Physics · mapped topic