Selective inhibition for selective metal deposition
US-12588435-B2 · Mar 24, 2026 · US
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Wajda Cory patents
Wajda Cory is listed as an inventor on 34 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wajda Cory |
| Total patents | 34 |
| First publication | Aug 6, 2015 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Thermal etching of ruthenium
US-12482667-B2 · Nov 25, 2025 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-12237216-B2 · Feb 25, 2025 · US
Thermal etching of ruthenium
US-2024153781-A1 · May 9, 2024 · US
Selective inhibition for selective metal deposition
US-2023274932-A1 · Aug 31, 2023 · US
Method for controlling the forming voltage in resistive random access memory devices
US-11700778-B2 · Jul 11, 2023 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-11621190-B2 · Apr 4, 2023 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-2022301930-A1 · Sep 22, 2022 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-2022139776-A1 · May 5, 2022 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-2021287936-A1 · Sep 16, 2021 · US
Recent patents
Latest publications not already listed above.
Method for controlling the forming voltage in resistive random access memory devices
US-2021234096-A1 · Jul 29, 2021 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-11024535-B2 · Jun 1, 2021 · US
Method for controlling the forming voltage in resistive random access memory devices
US-10991881-B2 · Apr 27, 2021 · US
Method utilizing using post etch pattern encapsulation
US-10950460-B2 · Mar 16, 2021 · US
Method for controlling the forming voltage in resistive random access memory devices
US-2020381624-A1 · Dec 3, 2020 · US
Ruthenium metal feature fill for interconnects
US-10700009-B2 · Jun 30, 2020 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-2020118871-A1 · Apr 16, 2020 · US
Method Utilizing Using Post Etch Pattern Encapsulation
US-2020051832-A1 · Feb 13, 2020 · US
Ruthenium metal feature fill for interconnects
US-2019103363-A1 · Apr 4, 2019 · US
Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization
US-10157784-B2 · Dec 18, 2018 · US
Selective metal oxide deposition using a self-assembled monolayer surface pretreatment
US-10068764-B2 · Sep 4, 2018 · US
Ruthenium metal feature fill for interconnects
US-10056328-B2 · Aug 21, 2018 · US
Method of corner rounding and trimming of nanowires by microwave plasma
US-10008564-B2 · Jun 26, 2018 · US
Selective metal oxide deposition using a self-assembled monolayer surface pretreatment
US-2018076027-A1 · Mar 15, 2018 · US
Ruthenium metal feature fill for interconnects
US-2017317022-A1 · Nov 2, 2017 · US
Ruthenium metal deposition method for electrical connections
US-2017241014-A1 · Aug 24, 2017 · US
Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization
US-2017236752-A1 · Aug 17, 2017 · US
Ruthenium metal feature fill for interconnects
US-9711449-B2 · Jul 18, 2017 · US
Method of corner rounding and trimming of nanowires by microwave plasma
US-2017125517-A1 · May 4, 2017 · US
Integration of ALD barrier layer and CVD Ru liner for void-free Cu filling
US-9607888-B2 · Mar 28, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tokyo Electron Ltd | 34 |
| IBM | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H01L21/76879 | 16 |
| H10W20/057 | 15 |
| H10P14/43 | 15 |
| H10W20/096 | 13 |
| H10W20/4432 | 11 |