Out-of-order fetch and decode pipelines
US-2026093493-A1 · Apr 2, 2026 · US
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Troester Kai patents
Troester Kai is listed as an inventor on 26 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Troester Kai |
| Total patents | 26 |
| First publication | Mar 22, 2016 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Retire queue compression
US-12204911-B2 · Jan 21, 2025 · US
Throttling while managing upstream resources
US-12032965-B2 · Jul 9, 2024 · US
Masked multi-lane instruction memory fault handling using fast and slow execution paths
US-11847463-B2 · Dec 19, 2023 · US
Fusing no-op (nop) instructions
US-2023315454-A1 · Oct 5, 2023 · US
Fastpath microcode sequencer
US-11467838-B2 · Oct 11, 2022 · US
Shared resource allocation in a multi-threaded microprocessor
US-11294724-B2 · Apr 5, 2022 · US
Throttling while managing upstream resources
US-2022058025-A1 · Feb 24, 2022 · US
Retire queue compression
US-2022027162-A1 · Jan 27, 2022 · US
Throttling while managing upstream resources
US-11169812-B2 · Nov 9, 2021 · US
Recent patents
Latest publications not already listed above.
Retire queue compression
US-11144324-B2 · Oct 12, 2021 · US
Soft watermarking in thread shared resources implemented through thread mediation
US-11144353-B2 · Oct 12, 2021 · US
Tracking stores and loads by bypassing load store units
US-11048506-B2 · Jun 29, 2021 · US
Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
US-11023241-B2 · Jun 1, 2021 · US
Throttling while managing upstream resources
US-2021096873-A1 · Apr 1, 2021 · US
Masked multi-lane instruction having both fast and slow execution paths
US-2021096857-A1 · Apr 1, 2021 · US
Soft watermarking in thread shared resources implemented through thread mediation
US-2021096914-A1 · Apr 1, 2021 · US
Shared resource allocation in a multi-threaded microprocessor
US-2021096920-A1 · Apr 1, 2021 · US
Retire queue compression
US-2021096874-A1 · Apr 1, 2021 · US
Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
US-2020065108-A1 · Feb 27, 2020 · US
Fastpath microcode sequencer
US-2019361699-A1 · Nov 28, 2019 · US
Tracking stores and loads by bypassing load store units
US-2019310845-A1 · Oct 10, 2019 · US
Tracking stores and loads by bypassing load store units
US-10331357-B2 · Jun 25, 2019 · US
Tracking stores and loads by bypassing load store units
US-2018052613-A1 · Feb 22, 2018 · US
Stack access tracking using dedicated table
US-9367310-B2 · Jun 14, 2016 · US
Stack access tracking
US-9292292-B2 · Mar 22, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 26 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3838 | 10 |
| G06F9/3836 | 9 |
| G06F9/3885 | 8 |
| G06F9/3856 | 8 |
| G06F9/30043 | 7 |