Stack access tracking

Patent metadata

Field	Value
Publication number	US-9292292-B2
Application number	US-201313922296-A
Country	US
Kind code	B2
Filing date	Jun 20, 2013
Priority date	Jun 20, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the entry of the stack accessed by the instruction stack relative to a base entry. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

First claim

What is claimed is:

1. A method comprising:
identifying, at an instruction pipeline of a processor, a first entry of a stack to be accessed by a first stack access instruction by identifying a first offset from a base of the stack based on the first stack access instruction;
identifying, at the instruction pipeline, a second entry of the stack to be accessed by a second stack access instruction by identifying a second offset from the base of the stack based on the second stack access instruction; and
identifying a dependency between the first stack access instruction and the second stack access instruction in response to the first offset matching the second offset.

2. The method of claim 1 , further comprising forwarding data from the first stack access instruction to the second stack access instruction to satisfy the second stack access instruction prior to moving the data from the instruction pipeline to memory in response to the first stack access instruction.

3. The method of claim 1 , wherein identifying the first offset comprises identifying the first offset based on a data size associated the first stack access instruction.

4. The method of claim 1 , wherein identifying the first offset comprises identifying the first offset based on a field of the first stack access instruction.

5. The method of claim 1 , further comprising:
storing identifiers of the first entry and the second entry at a table;
storing at the table an identifier of a first memory address associated with a first memory access instruction, the first memory access instruction being a non-stack-access instructions; and
identifying a dependency between the first memory access instruction and a second memory access instruction based on the identifier of the first memory address stored at the table.

6. The method of claim 5 , further comprising forwarding data from the first memory access instruction to the second memory access instruction in response to identifying the dependency between the first memory access instruction and the second memory access instruction.

7. The method of claim 1 , wherein the first stack access instruction comprises a push instruction and the second stack access instruction comprises a pop instruction.

8. The method of claim 1 , wherein identifying the first entry and the second entry comprises identifying the first entry and the second entry at a decode stage of the instruction pipeline.

9. A method, comprising:
predicting at an instruction pipeline that a first stack access instruction is dependent on a second stack access instruction based on offsets indicating predicted positions of a stack pointer after execution of the first stack access instruction and the second stack access instruction; and
in response to the prediction that the first stack access instruction is dependent on the second stack access instruction, forwarding data associated with the second stack access instruction to satisfy the first stack access instruction prior to moving the data from the instruction pipeline to memory external to the instruction pipeline.

10. The method of claim 9 , further comprising:
storing the offsets at a first table;
storing address register and offset information for non-stack-access instructions at the table; and
predicting dependencies between non-stack access instructions based on the table.

11. A processor comprising:
a cache; and
an instruction pipeline comprising:
a table to store identifiers for a first entry of a stack to be accessed by a first stack access instruction and a second entry of the stack to be accessed by a second stack access instruction, the identifiers comprising offsets from a base of the stack for the first stack access instruction and the second stack access instruction; and
a prediction module to predict a dependency between the first stack access instruction and the second stack access instruction in response to the offsets for the first stack access instruction and the second stack access instruction matching each other.

12. The processor of claim 11 , wherein the instruction pipeline further comprises a scheduler to forward data from the first stack access instruction to the second stack access instruction to satisfy the second stack access instruction prior to moving the data from the instruction pipeline to the cache in response to the first stack access instruction.

13. The processor of claim 11 , wherein:
the table is to store an identifier of a first memory address associated with a first memory access instruction, the first memory access instruction being a non-stack-access instruction; and
the prediction module is to predict a dependency between the first memory access instruction and a second memory access instruction based on the identifier of the first memory address stored at the table.

14. The processor of claim 13 , wherein the instruction pipeline further comprises a scheduler to forward data from the first memory access instruction to the second memory access instruction in response to the prediction of the dependency between the first memory access instruction and the second memory access instruction.

15. The processor of claim 12 , wherein the first stack access instruction comprises a push instruction and the second stack access instruction comprises a pop instruction.

Assignees

• Advanced Micro Devices Inc

Inventors

• Troester Kai
• Yen Luke

Classifications

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/38 Primary

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title