Retire queue compression

Patent metadata

Field	Value
Publication number	US-11144324-B2
Application number	US-201916586642-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Sep 27, 2019
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

First claim

What is claimed is:

1. A processor comprising:
a retire queue configured to store entries corresponding to instruction operations that have not been retired; and
control logic configured to:
receive a first instruction operation and a second instruction operation to be stored in the retire queue; and
compress the first instruction operation and the second instruction operation together into a single retire queue entry responsive to determining that the first instruction operation and the second instruction operation meet one or more conditions for being compressed together into a single retire queue entry.

2. The processor as recited in claim 1 , wherein the one or more conditions comprise:
a first condition that the first instruction operation and the second instruction operation are allowed to architecturally retire together, and
a second condition that all updates to an architectural state of the processor caused by the first instruction operation and the second instruction operation are able to be tracked in a single retire queue entry.

3. The processor as recited in claim 1 , wherein the one or more conditions comprise a condition that the first instruction operation and the second instruction operation were dispatched together.

4. The processor as recited in claim 1 , wherein the one or more conditions comprise a condition that the first instruction operation is older than the second instruction operation.

5. The processor as recited in claim 1 , wherein the one or more conditions comprise a condition that a program redirect is not able to occur in between the first instruction operation and the second instruction operation.

6. The processor as recited in claim 1 , wherein the control logic is further configured to store three or more instruction operations in a single retire queue entry responsive to determining that the three or more instruction operations meet the one or more conditions.

7. The processor as recited in claim 1 , wherein the processor is further configured to store an intermediate output of the first instruction operation in a reservation station entry rather than in a physical register.

8. A method comprising:
receiving a first instruction operation and a second instruction operation to be stored in the retire queue; and
compressing the first instruction operation and the second instruction operation together into a single retire queue entry responsive to determining that the first instruction operation and the second instruction operation meet one or more conditions for being compressed together into a single retire queue entry.

9. The method as recited in claim 8 , wherein the one or more conditions comprise:
a first condition that the first instruction operation and the second instruction operation are allowed to architecturally retire together, and
a second condition that all updates to a processor architectural state caused by the first instruction operation and the second instruction operation are able to be tracked in a single retire queue entry.

10. The method as recited in claim 8 , wherein the one or more conditions further comprise a condition that the first instruction operation and the second instruction operation were dispatched together.

11. The method as recited in claim 8 , wherein the one or more conditions comprise a condition that the first instruction operation is older than the second instruction operation.

12. The method as recited in claim 8 , wherein the one or more conditions further a condition that a program redirect is not able to occur in between the first instruction operation and the second instruction operation.

13. The method as recited in claim 8 , further comprising storing three or more instruction operations in a single retire queue entry responsive to determining that the three or more instruction operations meet the one or more conditions.

14. The method as recited in claim 8 , further comprising storing an intermediate output of the first instruction operation in a reservation station entry rather than in a physical register.

15. A system comprising:
a memory; and
a processor coupled to the memory;
wherein the processor is configured to:
receive a first instruction operation and a second instruction operation to be stored in a retire queue; and
compress the first instruction operation and the second instruction operation together into a single retire queue entry responsive to determining that the first instruction operation and the second instruction operation meet one or more conditions for being compressed together into a single retire queue entry.

16. The system as recited in claim 15 , wherein the one or more conditions comprise:
a first condition that the first instruction operation and the second instruction operation are allowed to architecturally retire together, and
a second condition that all updates to an architectural state of the processor caused by the first instruction operation and the second instruction operation are able to be tracked in a single retire queue entry.

17. The system as recited in claim 15 , wherein the one or more conditions comprise a condition that the first instruction operation and the second instruction operation were dispatched together.

18. The system as recited in claim 15 , wherein the one or more conditions comprise a condition that the first instruction operation is older than the second instruction operation.

19. The system as recited in claim 15 , wherein the one or more conditions comprise a condition that a program redirect is not able to occur in between the first instruction operation and the second instruction operation.

20. The system as recited in claim 15 , wherein the processor is further configured to store an intermediate output of the first instruction operation in a reservation station entry rather than in a physical register.

Assignees

• Advanced Micro Devices Inc

Inventors

• Sobel Matthew T
• Lindner Joshua James
• Marketkar Neil N
• Troester Kai
• Talpes Emil
• Venkatachar Ashok Tirupathy

Classifications

• G06F9/3858 Primary

  Result writeback, i.e. updating the architectural state or memory · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3854

  Instruction completion, e.g. retiring, committing or graduating · CPC title