Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines

Patent metadata

Field	Value
Publication number	US-11023241-B2
Application number	US-201816106515-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Aug 21, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.

First claim

What is claimed is:

1. A method, carried out by one or more processors, the method comprising:
receiving a load/store instruction into an address-generation-(AGEN)-bypass-determination unit (ABDU) of a processor;
routing the load/store instruction to an AGEN stage of the processor if an effective address for the load/store instruction is not known at the ABDU; and
routing the load/store instruction, to a load/store unit, to bypass the AGEN stage if the effective address for the load/store instruction is known at the ABDU wherein the effective address for the load/store instruction is known at the ABDU when each of a plurality of the effective-address inputs for the load/store instruction is known at the ABDU.

2. The method of claim 1 , wherein the effective address for the load/store instruction is known at the ABDU when the load/store instruction is a program-counter-(PC)-relative load/store instruction.

3. The method of claim 1 , wherein the effective address for the load/store instruction is known at the ABDU when the load/store instruction is a displacement-only load/store instruction.

4. The method of claim 1 , wherein the effective address for the load/store instruction is known at the ABDU when:
the load/store instruction is a stack-pointer-(SP)-relative load/store instruction; and
the ABDU has a current value of an SP register (rSP).

5. The method of claim 1 , wherein:
the AGEN stage is configured to compute the effective address for the load/store instruction using the plurality of effective-address inputs for the load/store instruction; and
the effective address for the load/store instruction is not known at the ABDU when at least one of the effective-address inputs for the load/store instruction is not known at the ABDU.

6. The method of claim 1 , wherein:
the processor further comprises:
the load/store unit;
a first circuit path that communicatively couples the ABDU and the load/store unit, and that includes the AGEN stage; and
a second circuit path that communicatively couples the ABDU and the load/store unit, and that bypasses the AGEN stage,

wherein:
routing the load/store instruction to the AGEN stage comprises routing the load/store instruction via the first circuit path; and
routing the load/store instruction to bypass the AGEN stage comprises routing the load/store instruction via the second circuit path.

7. The method of claim 6 , wherein:
routing the load/store instruction via the second circuit path comprises asserting a bypass- eligible flag that corresponds with the load/store instruction; and
the load/store unit is configured to:
process load/store instructions for which the corresponding bypass-eligible flag is asserted; and
discard load/store instructions for which the corresponding bypass-eligible flag is cleared.

8. The method of claim 6 , carried out by the processor with respect to a first integer number of load/store instructions per clock cycle, the method further comprising:
asserting a corresponding bypass-eligible flag for each load/store instruction that is routed via the second circuit path,
wherein the load/store unit is configured to:
process load/store instructions for which the corresponding bypass-eligible flag is asserted; and
discard load/store instructions for which the corresponding bypass-eligible flag is cleared.

9. The method of claim 8 , further comprising asserting a corresponding bypass-eligible flag for at most a second integer number of load/store instructions per clock cycle, wherein the second integer number is less than the first integer number.

10. The method of claim 9 , wherein the load/store unit has exactly the second integer number of load/store pipelines.

11. The method of claim 6 , wherein the load/store unit is configured to compute effective addresses for load/store instructions received by the load/store unit via the second circuit path.

12. The method of claim 1 , wherein:
the load/store instruction comprises a reference to a register; and
the method further comprises replacing the reference in the load/store instruction with a value currently stored in the register.

13. A processor comprising:
an address-generation (AGEN) stage; and
an AGEN-bypass-determination unit (ABDU) configured to:
receive a load/store instruction;
route the load/store instruction to the AGEN stage if an effective address for the load/store instruction is not known at the ABDU; and
route the load/store instruction, to a load/store unit, to bypass the AGEN stage if the effective address for the load/store instruction is known at the ABDU, wherein the effective address for the instruction is known at the ABDU when each of a plurality of the effective-address inputs for the load/store instruction is known at the ABDU.

14. The processor of claim 13 , wherein the effective address for the load/store instruction is known at the ABDU when the load/store instruction is a program-counter-(PC)-relative load/store instruction.

15. The processor of claim 13 , wherein the effective address for the load/store instruction is known at the ABDU when the load/store instruction is a displacement-only load/store instruction.

16. The processor of claim 13 , wherein the effective address for the load/store instruction is known at the ABDU when:
the load/store instruction is a stack-pointer-(SP)-relative load/store instruction; and
the ABDU has a current value of an SP register (rSP).

17. The processor of claim 13 , wherein:
the AGEN stage is configured to compute the effective address for the load/store instruction using the plurality of effective-address inputs for the load/store instruction; and
the effective address for the load/store instruction is not known at the ABDU when at least one of the effective-address inputs for the load/store instruction is not known at the ABDU.

18. The processor of claim 13 , further comprising:
the load/store unit;
a first circuit path that communicatively couples the ABDU and the load/store unit, and that includes the AGEN stage; and
a second circuit path that communicatively couples the ABDU and the load/store unit, and that bypasses the AGEN stage,
wherein the ABDU is configured to:
route the load/store instruction to the AGEN stage via the first circuit path; and
route the load/store instruction to bypass the AGEN stage via the second circuit path.

19. The processor of claim 18 , wherein:
the ABDU is configured to assert a bypass-eligible flag that corresponds with the load/store instruction when routing the load/store instruction via the second circuit path; and
the load/store unit is configured to:
process load/store instructions for which the corresponding bypass-eligible flag is asserted; and
discard load/store instructions for which the corresponding bypass-eligible flag is cleared.

20. The processor of claim 18 , further configured to:
route each of a first integer number of load/store instructions per clock cycle via either the first circuit path or the second circuit path; and
assert a corresponding bypass-eligible flag for each load/store instruction that is routed via the second circuit path,
wherein the load/store unit is configured to:
process load/store instructions for which the corresponding bypass-eligible flag is asserted; and
discard load/store instructions for which the corresponding bypass-eligible flag is cleared.

21. The processor of claim 20 , further configured to assert a corresponding bypass-eligible flag for at most a secon

Assignees

• Advanced Micro Devices Inc

Inventors

• Kocev Andrej
• Fleischman Jay
• Troester Kai
• Chu Johnny C
• Wilkens Tim J
• Marketkar Neil
• Long Michael W

Classifications

• G06F9/3826 Primary

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/321

  Program or instruction counter, e.g. incrementing · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3832

  Value prediction for operands; operand history buffers · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title