Tracking stores and loads by bypassing load store units

Patent metadata

Field	Value
Publication number	US-11048506-B2
Application number	US-201916450897-A
Country	US
Kind code	B2
Filing date	Jun 24, 2019
Priority date	Aug 19, 2016
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.

First claim

What is claimed is:

1. A method for predicting dependent store-load pairs to reduce load latency when storing and loading from a same memory address by bypassing a load store (LS) unit within an execution unit, the method comprising:
inputting load and store instruction information from a micro operation queue;
comparing load instruction information to values in a prediction table and outputting the comparison to a predictor logic;
comparing store instruction information to values in the prediction table;
determining if the store is valid based on values in the prediction table and outputting a store validity determination and the store comparison to the predictor logic;
determining a confidence value and providing an indication of the confidence value to the predictor logic; and
providing memory dependency predictor information from the predictor logic to a memory renaming unit.

2. The method of claim 1 , wherein the input load and store instruction information is used to identify the respective load and store instructions.

3. The method of claim 1 , wherein the input load and store instruction information comprises a fetch address of the store.

4. The method of claim 1 , wherein the input load and store instruction information comprises a fetch address of the load.

5. The method of claim 1 , wherein the prediction table has been trained through the LS unit.

6. The method of claim 1 , further comprising linking the load to the store in the memory renaming unit.

7. A system for predicting dependent store-load pairs to reduce load latency when storing and loading from a same memory address by bypassing a load store (LS) unit within an execution unit, the system comprising:
a micro operation queue configured to dispatch load or store operations;
one or more predictive units configured to identify conditions where a load/store unit is bypassed and memory renaming is utilized for at least one of the load or store operations; and
a memory renaming unit configured to operate to cause the at least one of the load or store operations to be renamed.

8. The system of claim 7 , further comprising a floating point renamer that renames the at least one of the load or store operations.

9. The system of claim 7 , further comprising an integer renamer that renames the at least one of the load or store operations.

10. The system of claim 7 , wherein the dispatched load or store operation is used to identify the respective load and store.

11. The system of claim 7 , wherein a dispatched load or store information comprises a fetch address of the store.

12. The system of claim 7 , wherein a dispatched load or store information comprises a fetch address of the load.

13. The system of claim 7 , wherein the predictive unit includes at least one prediction table.

14. The system of claim 7 , wherein the predictive unit has been trained through the LS unit.

15. The system of claim 7 , further comprising linking the load to the store in the memory renaming unit.

16. A method for performing training of a prediction table used for predicting dependency of stores and loads to reduce load latency when storing and loading from a same memory address by bypassing a load store (LS) unit within an execution unit, the method comprising:
inputting load and store instruction information from the load store unit;
providing an indication of an acceptance of store to load forwarding to a confidence counter update logic;
comparing load instruction information to values in the prediction table and outputting the comparison to the confidence counter update logic;
comparing store instruction information to values in the prediction table and outputting the comparison to the confidence counter update logic;
determining a confidence value and providing an indication of the confidence value to the confidence counter update logic; and
updating entry in a confidence field of the prediction table based on feedback from the confidence counter update logic.

17. The method of claim 16 , wherein the input load and store instruction information is used to identify the respective load and store instruction.

18. The method of claim 16 , wherein the input load and store instruction information comprises a fetch address of the store.

19. The method of claim 16 , wherein the input load and store instruction information comprises a fetch address of the load.

20. The method of claim 16 , wherein the prediction table has been trained through the LS unit.

21. A method of memory renaming to reduce load latency when storing and loading from a same memory address by bypassing a load store (LS) unit within an execution unit, the method comprising:
implementing a load store forwarding prediction mechanism in a decode unit of a processor;
maintaining data stored by the store in the execution unit using a register file based in the implemented prediction mechanism;
directing a dependent load to utilize the maintained data to bypass the LS unit; and
providing correction if the prediction mechanism is incorrect in the prediction.

Assignees

• Advanced Micro Devices Inc

Inventors

• Ramani Krishnan V
• Troester Kai
• Galloway Frank C
• Suggs David N
• Achenbach Michael D
• Mcdaniel Betty Ann
• Evers Marius

Classifications

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/28 Primary

  Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title