Asymmetric gate extension in stacked FET

Patent metadata

Field	Value
Publication number	US-12446290-B2
Application number	US-202318302021-A
Country	US
Kind code	B2
Filing date	Apr 18, 2023
Priority date	Apr 18, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a stack of transistors with a first transistor on top of a second transistor, wherein a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width,
wherein the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, the first side being opposite the second side.

2. The semiconductor structure of claim 1 , wherein the second gate extensions of the first and the second transistor at the second side of the stack are conformal, and the second gate extension of the first transistor conformally extends into the second gate extension of the second transistor.

3. The semiconductor structure of claim 1 , wherein the gate of the first transistor vertically aligns with the gate of the second transistor at the first side of the stack.

4. The semiconductor structure of claim 1 , wherein the first and the second transistor are a first and a second nanosheet transistor having a first and a second set of nanosheets respectively, and the first width of the gate of the first transistor equals to a width of the first set of nanosheets and the second width of the gate of the second transistor equals to a width of the second set of nanosheets.

5. The semiconductor structure of claim 4 , wherein the first set of nanosheets are vertically separated by a distance ranging from about 6 nm to about 20 nm.

6. The semiconductor structure of claim 1 , wherein the stack of transistors is a first stack of transistors, further comprising:
a second stack of transistors with a third transistor on top of a fourth transistor, wherein a gate of the third transistor has a third width; a gate of the fourth transistor has a fourth width; and the third width is narrower than the fourth width,
wherein the second stack of transistors being opposite the first side of the first stack of transistors, and wherein the third and the fourth transistor respectively have a third gate extension at a first side of the second stack and a fourth gate extension at a second side of the second stack, the third gate extension at the first side of the second stack being narrower than the fourth gate extension at the second side of the second stack, the second side of the second stack being opposite the first side of the second stack.

7. The semiconductor structure of claim 6 , wherein the first gate extensions of the first and the second transistor are separated from the third gate extensions of the third and the fourth transistor by a dielectric pillar, the dielectric pillar having a width ranging from about 5 nm to about 50 nm.

8. The semiconductor structure of claim 6 , wherein the first gate extension and the third gate extension have a substantially same first width, and the second gate extension and the fourth gate extension have a substantially same second width, the first width of the first gate extension being narrower than the second width of the second gate extension.

9. A method of forming a semiconductor structure comprising:
forming a stack of nanosheets including a first set of nanosheets on top of a second set of nanosheets, the first set of nanosheets having a first width, the second set of nanosheets having a second width, and the first width being narrower than the second width; and
forming a first gate extension on a first side of the stack of nanosheets and a second gate extension on a second side of the stack of nanosheets, the first side being opposite the second side, and the first gate extension being narrower than the second gate extension.

10. The method of claim 9 , wherein forming the first gate extension and the second gate extension comprises:
forming a first extension placeholder at the first side of the stack of nanosheets and a second extension placeholder at the second side of the stack of nanosheets; and
replacing the first extension placeholder with the first gate extension and the second extension placeholder with the second gate extension in a replacement-metal-gate process.

11. The method of claim 10 , wherein forming the first extension placeholder and the second extension placeholder comprises:
forming a first raw placeholder layer at the second side of the stack of nanosheets;
forming a second raw placeholder layer at the first side of the stack of nanosheets and at the second side of the stack of nanosheets over the first raw placeholder layer;
patterning the second raw placeholder layer at the first side of the stack of nanosheets to form the first extension placeholder; and
patterning the first and the second raw placeholder layer at the second side of the stack of nanosheets to form the second extension placeholder.

12. The method of claim 10 , wherein forming the first extension placeholder and the second extension placeholder comprises:
forming a first raw placeholder layer at the first and the second side of the stack of nanosheets;
forming a second raw placeholder layer at the second side of the stack of nanosheets over the first raw placeholder layer;
patterning the first raw placeholder layer at the first side of the stack of nanosheets to form the first extension placeholder; and
patterning the first and the second raw placeholder layer at the second side of the stack of nanosheets to form the second extension placeholder.

13. The method of claim 9 , wherein forming the stack of nanosheets comprises:
forming a second set of raw nanosheets on a semiconductor substrate, the second set of raw nanosheets are separated by a second set of raw suspension sheets;
forming a sacrificial insulation sheet above the second set of raw nanosheets;
forming a first set of raw nanosheets above the sacrificial insulation sheet, the first set of raw nanosheets are separated by a first set of raw suspension sheets; and
patterning the first and the second set of raw nanosheets to create the first and the second set of nanosheets in a selective etching process.

14. The method of claim 13 , further comprising:
removing the sacrificial insulation sheet in a selective etching process to create an opening between the first and the second set of raw nanosheets; and
forming a raw insulation sheet by depositing a dielectric material in the opening,
wherein the first and the second set of raw suspension sheets are silicon-germanium (SiGe) sheets having a first germanium (Ge) concentration level and the sacrificial insulation sheet is a SiGe sheet having a second Ge concentration level, the second Ge concentration level being larger than the first Ge concentration level.

15. The method of claim 9 , wherein the stack of nanosheets is a first stack of nanosheets, further comprising:
forming a second stack of nanosheets opposite the first side of the first stack of nanosheets,
wherein the second stack of nanosheets includes a third set of nanosheets on top of a fourth set of nanosheets, the third set of nanosheets having a third width, the fourth set of nanosheets having a fourth width, the third width being narrower than the fourth width.

16. A semiconductor structure comprising:
a first stack of transistors with a first transistor on top of a second transistor, wherein a gate of the first transistor has a first width, and a gate of the second transistor has a second width, with the first width being narrower than the sec

Assignees

• IBM

Inventors

• Xie Ruilong
• Anderson Brent A
• Wang Junli
• Strane Jay William
• Chu Albert M

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D88/01 Primary

  Manufacture or treatment · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title