CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor

Patent metadata

Field	Value
Publication number	US-12310090-B2
Application number	US-202318093932-A
Country	US
Kind code	B2
Filing date	Jan 6, 2023
Priority date	Mar 24, 2020
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

First claim

The invention claimed is:

1. A method, comprising:
forming a p-type field effect transistor region including a p-type bottom source/drain and one or more first vertical fins and an n-type field effect transistor region including an n-type bottom source/drain and one or more second vertical fins, onto a semiconductor substrate;
forming a top spacer on each of the one or more first vertical fins and the one or more second vertical fins;
forming a p-type top source/drain on the one or more first vertical fins of the p-type field effect transistor region by:
performing a first step of ion implanting of p-type dopants relative to exposed segments of the one or more first vertical fins;
epitaxially growing one or more p-type source/drain layers on the top spacer and on the exposed segments of the one or more first vertical fins; and
performing a second step of ion implanting of p-type dopants into the one or more p-type source/drain layers;

forming an n-type top source/drain on the one or more second vertical fins of the n-type field effect transistor region by:
performing a first step of ion implanting of n-type dopants relative to exposed segments of the one or more second vertical fins;
epitaxially growing one or more n-type source/drain layers on the top spacer and on the exposed segments of the one or more second vertical fins; and
performing a second step of ion implanting of n-type dopants into the one or more n-type source/drain layers; and
depositing a sacrificial fill material, comprising amorphous silicon, onto the top spacer disposed on the one or more second vertical fins prior to forming the p-type top source/drain, and exposing the sacrificial fill material to at least the first step of ion implanting of p-type dopants.

2. The method of claim 1 further including exposing the sacrificial fill material to the second step of ion implanting of p-type dopants.

3. The method of claim 2 further including removing the sacrificial fill material from the top spacer on the one or more second vertical fins prior to forming the n-type top source/drain on the one or more second vertical fins.

4. The method of claim 3 including forming a dielectric layer on the p-type field effect transistor region to cover the p-type top source/drain on the one or more first vertical fins prior to forming the n-type top source/drain on the one or more second vertical fins.

5. The method of claim 4 wherein depositing the sacrificial fill material includes depositing sacrificial fill material on the top spacer on the one or more first vertical fins.

6. The method of claim 5 including removing the sacrificial fill material from the top spacer of the one or more first vertical fins prior to forming the p-type top source/drain.

7. The method of claim 6 wherein removing the sacrificial fill material from the top spacer of the one or more first vertical fins includes:
depositing a liner over the p-type field effect transistor region and the n-type field effect transistor region;
patterning the liner to expose the p-type field effect transistor region; and
etching the sacrificial fill material from the top spacer on the one or more first vertical fins.

8. The method of claim 4 including forming a liner on the p-type field effect transistor region to cover the p-type top source/drain on the one or more first vertical fins prior to forming dielectric layer, the liner comprising a different material than a material of the dielectric layer.

9. The method of claim 8 wherein forming the liner and forming the dielectric layer includes extending the liner and the dielectric layer to cover the n-type field effect transistor region.

10. The method of claim 9 further including patterning the liner and the dielectric layer to expose the n-type field effect transistor region prior to forming the n-type top source/drain on the one or more second vertical fins.

11. The method of claim 1 wherein the p-type field effect transistor region includes at least two first vertical fins and the n-type field effect transistor region includes at least two second vertical fins.

12. A method, comprising:
forming a p-type field effect transistor region including a p-type bottom source/drain and a plurality of first vertical fins and an n-type field effect transistor region including an n-type bottom source/drain and a plurality of second vertical fins onto a semiconductor substrate;
forming a top spacer on each of the first vertical fins and the second vertical fins;
forming a p-type top source/drain on each of the first vertical fins by:
performing a first step of ion implanting of p-type dopants relative to exposed segments of the first vertical fins;
epitaxially growing a p-type source/drain layer on the top spacer on the exposed segments of the first vertical fins; and
performing a second step of ion implanting of p-type dopants into the p-type source/drain layer;

depositing a sacrificial fill material, comprising amorphous silicon, onto the top spacer of the second vertical fins;
exposing the sacrificial fill material to the first and second steps of ion implanting of p-type dopants;
removing the sacrificial fill material; and
forming n-type top source/drains on exposed segments of the second vertical fins.

13. The method of claim 12 including forming a dielectric layer on the p-type field effect transistor region to cover the p-type top source/drain on each of the first vertical fins prior to forming the n-type top source/drains.

14. The method of claim 13 wherein forming the n-type top source/drains includes:
performing a first step of ion implanting of n-type dopants relative to exposed segments of the second vertical fins;
epitaxially growing an n-type source/drain layer on exposed segments of the second vertical fins; and
performing a second step of ion implanting of n-type dopants into the n-type source/drain layers.

15. The method of claim 14 including forming a metal gate about each of the first vertical fins and the second vertical fins.

16. A method, comprising:
forming a first-type field effect transistor region including a first-type bottom source/drain and a plurality of first vertical fins and a second-type field effect transistor region including a second-type bottom source/drain and a plurality of second vertical fins onto a semiconductor substrate;
depositing a sacrificial fill material, comprising amorphous silicon, onto the first vertical fins and the second vertical fins;
removing the sacrificial fill material from the first vertical fins to expose segments of the first vertical fins;
forming a first-type top source/drain on each of the first vertical fins by:
performing a first step of ion implanting of first-type dopants into the exposed segments of the first vertical fins;
epitaxially growing a first-type source/drain layer on each of the exposed segments of the first vertical fins; and
performing a second step of ion implanting of first-type dopants into the first-type source/drain layers to form the first-type top source/drains;

covering the first-type field effect transistor region including the first-type top source/drain on each of the first vertical fins with a mask layer;
removing the sacrificial fill material from the second vertical fins to expose segments of the second vertical fins; and
forming a second-type top source/drain on each of the second vertical fins.

17. The method of claim 16 wherein forming the second-type top source/drain on each of the second vertical fins includes:
performing a first step of ion implanting of second

Assignees

• IBM

Inventors

• Wu Heng
• Xie Ruilong
• Fan Su Chen
• Strane Jay William
• Jagannathan Hemanth

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P30/22

  using masks · CPC title

• H10D84/8316

  the IGFETs characterised by having gate sidewall spacers specially adapted for integration · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0195

  the components including vertical IGFETs · CPC title